> memory_order_release meaningful, but somewhat different from the
non-fence
it would be nice to have release fence with an artificial dependency
to define a set of actually release stores and not constraining other
subsequent stores (and the order of release stores with respect to
each other), e.
> atomic_thread_fence(memory_order_acquire)
int r1 = x; // ordinary load
int r2 = y.load(memory_order_relaxed); // atomic relaxed load
if (z.load(memory_order_relaxed) == SOMETHING_I_AM_WAITING_FOR) {
atomic_thread_fence(memory_order_acquire);
.
.
.
}
IIUC r1 and r2 (and etc.) loads
