On Mon, 8 Nov 2021 11:17:47 GMT, Fei Yang wrote:
> This PR implements JEP 422: Linux/RISC-V Port [1].
> The PR starts as a squashed merge of the
> https://openjdk.java.net/projects/riscv-port branch.
>
> This has been tested with jtreg tier{1,2,3,4} and jcstress on HiFive
&g
On Wed, 23 Mar 2022 02:17:22 GMT, Vladimir Kozlov wrote:
>> Fei Yang has updated the pull request incrementally with one additional
>> commit since the last revision:
>>
>> Fix copyright header
>
> Update looks good.
> Testing results are also good.
08 benchmark tests are also
> carried out regularly. So it should be good enough to run most Java programs.
>
> [1] https://openjdk.java.net/jeps/422
Fei Yang has updated the pull request with a new target base due to a merge or
a rebase. The incremental webrev excludes the unrelated
On Wed, 23 Mar 2022 01:57:25 GMT, Fei Yang wrote:
>> src/hotspot/cpu/riscv/disassembler_riscv.hpp line 18:
>>
>>> 16: *
>>> 17: * You should have received a copy of the GNU General Public License
>>> version
>>> 18: * 2 along wi
On Tue, 22 Mar 2022 17:34:18 GMT, Vladimir Kozlov wrote:
>> Fei Yang has updated the pull request incrementally with one additional
>> commit since the last revision:
>>
>> Address review comments
>
> src/hotspot/cpu/riscv/disassembler_riscv.hpp line 18:
>
On Tue, 22 Mar 2022 14:01:28 GMT, Roger Riggs wrote:
> The test/jdk files look ok. (I didn't look at the rest)
Thank you for looking at that part.
-
PR: https://git.openjdk.java.net/jdk/pull/6294
08 benchmark tests are also
> carried out regularly. So it should be good enough to run most Java programs.
>
> [1] https://openjdk.java.net/jeps/422
Fei Yang has updated the pull request incrementally with one additional commit
since the last revision:
Fix copyright header
On Tue, 22 Mar 2022 04:13:17 GMT, David Holmes wrote:
>> Fei Yang has updated the pull request with a new target base due to a merge
>> or a rebase. The incremental webrev excludes the unrelated changes brought
>> in by the merge/rebase. The pull request contains two
On Tue, 22 Mar 2022 05:12:46 GMT, David Holmes wrote:
> Hi,
>
> I've looked at everything that is not a RISC-V specific file, except for the
> C1 changes as the compiler folk will need to approve those.
>
> Some copyrights will need updating to 2022 on the Oracle copyright line
> please.
Hi
On Tue, 22 Mar 2022 03:31:16 GMT, Fei Yang wrote:
>> This PR implements JEP 422: Linux/RISC-V Port [1].
>> The PR starts as a squashed merge of the
>> https://openjdk.java.net/projects/riscv-port branch.
>>
>> This has been tested with jtreg tier{1,2,3,4} and jc
08 benchmark tests are also
> carried out regularly. So it should be good enough to run most Java programs.
>
> [1] https://openjdk.java.net/jeps/422
Fei Yang has updated the pull request incrementally with one additional commit
since the last revision:
Address review comments
08 benchmark tests are also
> carried out regularly. So it should be good enough to run most Java programs.
>
> [1] https://openjdk.java.net/jeps/422
Fei Yang has updated the pull request with a new target base due to a merge or
a rebase. The incremental webrev excludes the unrelated
On Mon, 8 Nov 2021 11:17:47 GMT, Fei Yang wrote:
> This PR implements JEP 422: Linux/RISC-V Port [1].
> The PR starts as a squashed merge of the
> https://openjdk.java.net/projects/riscv-port branch.
>
> This has been tested with jtreg tier{1,2,3,4} and jcstress on HiFive
&g
This PR implements JEP 422: Linux/RISC-V Port [1].
The PR starts as a squashed merge of the
https://openjdk.java.net/projects/riscv-port branch.
This has been tested with jtreg tier{1,2,3,4} and jcstress on HiFive Unmatched
board. Dacapo, SPECjbb2015 and SPECjvm2008 benchmark tests are also carr
On Wed, 16 Sep 2020 16:36:54 GMT, Fei Yang wrote:
> Contributed-by: ard.biesheu...@linaro.org, dong...@huawei.com
>
> This added an intrinsic for SHA3 using aarch64 v8.2 SHA3 Crypto Extensions.
> Reference implementation for core SHA-3 transform using ARMv8.2 Crypto
> Exte
On Thu, 22 Oct 2020 03:59:45 GMT, Vladimir Kozlov wrote:
> tier1,2,3 passed. I verified that new SHA3 tests were run and passed.
> But because SHA3 is not enabled for now (even on aarch64), it does not test
> asm code.
> At least testing verified that changes in shared code does not cause any
>
On Wed, 21 Oct 2020 19:20:28 GMT, Vladimir Kozlov wrote:
>> OK. Will update with the following change after Aleksey's PR is integrated:
>>
>> ---
>> a/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot.test/src/org/graalvm/compiler/hotspot/test/CheckGraalIntrinsics.java
>>
automatically for aarch64. We can
> auto-enable this when it is fully tested on real hardware. But for the above
> testing purposes, this is auto-enabled when the corresponding hardware
> feature is detected.
Fei Yang has updated the pull request incrementally with one
On Tue, 20 Oct 2020 23:08:22 GMT, Vladimir Kozlov wrote:
> Someone in Oracle have to run tier1-tier3 testing with these changes to make
> sure nothing is broken. I don't want to repeat 8254790.
That's appreciated.
On my side, I run tier1-tier3 both on aarch64 linux and x86_64 linux.
The test re
On Tue, 20 Oct 2020 23:06:41 GMT, Vladimir Kozlov wrote:
>> Fei Yang has updated the pull request with a new target base due to a merge
>> or a rebase. The pull request now contains 13 commits:
>>
>> - Fix trailing whitespace issue reported by jcheck
>> - M
matically for aarch64. We can
> auto-enable this when it is fully tested on
> real hardware. But for the above testing purposes, this is auto-enabled when
> the corresponding hardware feature is
> detected.
Fei Yang has updated the pull request with a new target base due to a merge or
a
On Mon, 19 Oct 2020 20:26:22 GMT, Vladimir Kozlov wrote:
> Always run graalunit testing with new intrinsics. You need to adjust Graal
> test:
> src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.hotspot.test/src/org/graalvm/compiler/hotspot/test/CheckGraalIntrinsics.java
Thanks for
matically for aarch64. We can
> auto-enable this when it is fully tested on
> real hardware. But for the above testing purposes, this is auto-enabled when
> the corresponding hardware feature is
> detected.
Fei Yang has updated the pull request with a new target base due to
matically for aarch64. We can
> auto-enable this when it is fully tested on
> real hardware. But for the above testing purposes, this is auto-enabled when
> the corresponding hardware feature is
> detected.
Fei Yang has updated the pull request incrementally with one additional c
matically for aarch64. We can
> auto-enable this when it is fully tested on
> real hardware. But for the above testing purposes, this is auto-enabled when
> the corresponding hardware feature is
> detected.
Fei Yang has updated the pull request incrementally with one additional commit
matically for aarch64. We can
> auto-enable this when it is fully tested on
> real hardware. But for the above testing purposes, this is auto-enabled when
> the corresponding hardware feature is
> detected.
Fei Yang has updated the pull request with a new target base due to a merge o
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