tnx but i know this !
I try to explain (sorry for the english)
I have made a pirq table as show into the web page of the linuxbios.org with
a kernel 2.6.23. The routing table made for the motherboard work, the
request are signaled to the kernel and after to the driver better.
With the same pirq
On 15.01.2008 18:54, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
The BKDG rev. 3.08 for AMD Family 0Fh states that it is possible to use
a CAR area with a size of 64K in section 13.16 Cache Initialization For
General Storage During Boot. It also says that during DRAM training CAR
size
Author: stepan
Date: 2008-01-16 15:40:04 +0100 (Wed, 16 Jan 2008)
New Revision: 41
Modified:
trunk/filo-0.5/fs/filesys.h
trunk/filo-0.5/fs/vfs.c
Log:
hook up cramfs and squashfs
Modified: trunk/filo-0.5/fs/filesys.h
===
---
Looks good, but a few comments:
On Wed, Jan 16, 2008 at 12:34:14PM +0100, Patrick Georgi wrote:
the attached patch makes cbv2 add information about the serial port to
lbtable. For this, a new record type is created. Payloads can then parse
lbtable to figure out where to find the serial port
* Uwe Hermann [EMAIL PROTECTED] [080116 16:03]:
Looks good, but a few comments:
On Wed, Jan 16, 2008 at 12:34:14PM +0100, Patrick Georgi wrote:
the attached patch makes cbv2 add information about the serial port to
lbtable. For this, a new record type is created. Payloads can then parse
On Jan 16, 2008 4:10 AM, Cimino Vittorio [EMAIL PROTECTED] wrote:
I have made a pirq table as show into the web page of the linuxbios.org with
a kernel 2.6.23. The routing table made for the motherboard work, the
request are signaled to the kernel and after to the driver better.
With the
ron minnich wrote:
It seems like you've added two slightly more complicated ways to do
things where one simple one would have done: an end-of-entries LAR
header. Limiting payload segments to two is going to cause us trouble
now and forever, I think. And I'd still like to have a microcode/
On 16.01.2008 21:58, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
As I understand the logic of the snippet above, we look for a DQSWrDelay
which does not give any errors with TrainReadDQS. Then we don't care
about errors for other values of DQSWrDelay and use the current value of
On Thu, Jan 17, 2008 at 01:24:38AM +0100, Carl-Daniel Hailfinger wrote:
Please be aware that the M57SLI may read the reset vector and other
really early stuff at 33 MHz, thereby causing read errors
(sometimes single bit shifts) which are really hard to find.
English translation:
SST25VF016B
On Thu, Jan 17, 2008 at 03:03:48AM +0100, Peter Stuge wrote:
On Wed, Jan 16, 2008 at 08:57:52PM -0500, Ward Vandewege wrote:
English translation:
SST25VF016B is not really compatible with the IT8716F superio.
All right. So how about the Atmel AT45DB321D-SU
Unfortunately it has a
On 17.01.2008 02:48, Ward Vandewege wrote:
Hi Ronald,
On Thu, Jan 17, 2008 at 12:13:48AM +0100, Ronald Hoogenboom wrote:
Problem1 (for reading) is solved by NOT using the mmap method for
reading the flash contents, but using outb() for sending the flash read
commands (using a specific
Author: rminnich
Date: 2008-01-17 06:37:41 +0100 (Thu, 17 Jan 2008)
New Revision: 555
Added:
coreboot-v3/northbridge/amd/geodelx/dts
Modified:
coreboot-v3/mainboard/pcengines/alix1c/dts
Log:
This change adds a dts file for the amd geodelx northbridge. The
northbridge has several
This is the beginning of a set of needed changes to get the geode
running. Comments welcome.
I'll hold off on further patches until people get a look at this and
see if it is ok.
Thanks!
ron
This change is for tidying up some unfinished business in the device code.
I just uncovered this
13 matches
Mail list logo
