can you assist to port on the tyan motherboard
lspci
00:01.0 PCI bridge: Broadcom HT1000 PCI/PCI-X bridge
00:02.0 Host bridge: Broadcom HT1000 Legacy South Bridge
00:02.1 IDE interface: Broadcom HT1000 Legacy IDE controller
00:02.2 ISA bridge: Broadcom HT1000 LPC Bridge
00:03.0 USB Controller:
ron minnich wrote:
We need to start a program. I am thinking I might do a section on
anatomy of the v3 port to LX.
I wonder if any AMD folks could talk about issues relevant to AMD.
We would be happy to. Did you have something specific in mind? For the
most part it will be the same
Author: myles
Date: 2008-02-07 17:50:44 +0100 (Thu, 07 Feb 2008)
New Revision: 578
Added:
coreboot-v3/mainboard/emulation/qemu-x86/defconfig
Modified:
coreboot-v3/Makefile
coreboot-v3/util/kconfig/confdata.c
coreboot-v3/util/kconfig/symbol.c
Log:
This patch adds support for make
Author: myles
Date: 2008-02-07 17:50:44 +0100 (Thu, 07 Feb 2008)
New Revision: 578
Added:
coreboot-v3/mainboard/emulation/qemu-x86/defconfig
Modified:
coreboot-v3/Makefile
coreboot-v3/util/kconfig/confdata.c
coreboot-v3/util/kconfig/symbol.c
Log:
This patch adds support for make
Signed-off-by: Myles Watson [EMAIL PROTECTED]
Acked-by: Ward Vandewege [EMAIL PROTECTED]
Thanks,
Rev 578
Myles
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On Thu, Feb 07, 2008 at 09:26:32AM -0700, Myles Watson wrote:
This patch adds support for make defconfig in v3. Those that port v3
to a board should add a defconfig in mainboard/vendor/board/defconfig.
I think that the defconfig should:
1. Use the ROM size that comes with the board
2.
On Thu, Feb 07, 2008 at 10:03:14AM -0700, Myles Watson wrote:
Does this look good enough for an ack? I know you already ack'ed several
previous revisions of this patch, but it's probably best if I don't commit
this without a formal ack of the latest revision :)
Thanks,
Ward.
Sorry,
On Feb 7, 2008 12:45 PM, Marc Karasek [EMAIL PROTECTED] wrote:
Let me add me two cents..
I have dealt with the Intel MACs in the past so let me dreg up some
memorries...
From what I recall, you had a serial eeprom on the board that
contained the init for the chip. This was the 82545GM.
-Original Message-
From: Ward Vandewege [mailto:[EMAIL PROTECTED]
Sent: Thursday, February 07, 2008 1:44 PM
To: Myles Watson
Cc: Coreboot
Subject: Re: Buildrom v3 config patch and qemu rename patch
On Thu, Feb 07, 2008 at 01:33:38PM -0700, Myles Watson wrote:
This patch
On Feb 7, 2008 1:32 PM, Stefan Reinauer [EMAIL PROTECTED] wrote:
* Myles Watson [EMAIL PROTECTED] [080207 20:54]:
Signed-off-by: Myles Watson [EMAIL PROTECTED]
Acked-by: Stefan Reinauer [EMAIL PROTECTED]
Thanks,
Rev 3093
Myles
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On Thu, Feb 07, 2008 at 01:33:38PM -0700, Myles Watson wrote:
This patch changes buildrom for the renaming of qemu-i386 to qemu-x86.
It also adds make coreboot-v3-config support ala Ward. Ward, could
you check to make sure I didn't do something dumb when I shamelessly
copied you?
Heh :)
Author: myles
Date: 2008-02-07 21:37:37 +0100 (Thu, 07 Feb 2008)
New Revision: 3093
Added:
trunk/coreboot-v2/src/cpu/emulation/qemu-x86/
trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/
trunk/coreboot-v2/targets/emulation/qemu-x86/
Removed:
This patch changes buildrom for the renaming of qemu-i386 to qemu-x86.
It also adds make coreboot-v3-config support ala Ward. Ward, could
you check to make sure I didn't do something dumb when I shamelessly
copied you?
Thanks,
Myles
Signed-off-by: Myles Watson [EMAIL PROTECTED]
Index:
* Myles Watson [EMAIL PROTECTED] [080207 20:54]:
Signed-off-by: Myles Watson [EMAIL PROTECTED]
Acked-by: Stefan Reinauer [EMAIL PROTECTED]
Index: src/cpu/emulation/qemu-i386/northbridge.c
===
---
* ron minnich [EMAIL PROTECTED] [080207 08:46]:
This is a subtle problem.
Devices must have constructor struct members to be used.
static struct device_operations southbridge_ops = {
+ .constructor= default_device_constructor,
Before we start doing this all
ron minnich wrote:
On Feb 7, 2008 11:27 AM, Marc Jones [EMAIL PROTECTED] wrote:
You need good settings for the southbridge in your platform dts. You
should be able to copy these from v2.
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = 0;
/*
On Feb 7, 2008 11:16 AM, Marc Jones [EMAIL PROTECTED] wrote:
I preferred the v2 way of doing this. If the AMD IDE device was found it
got initialized. I think it needs a DTS and I think other southbridges
with multiple PCI headers will need this too.
So it's more like the northbridge part as
Lar does not currently process bss quite right.
I kind of blame ELF, but see what you think.
Here is filo. These are program headers used in Execution (the 'E' in ELF):
LOAD 0xc0 0x0010 0x0010 0x11430 0x36890 RWE 0x20
LOAD 0x011500 0x001368a0 0x001368a0
This patch adds support for make defconfig in v3. Those that port v3
to a board should add a defconfig in mainboard/vendor/board/defconfig.
I think that the defconfig should:
1. Use the ROM size that comes with the board
2. Enable compression
3. Not include a payload
This will make it easy for
We need to start a program. I am thinking I might do a section on
anatomy of the v3 port to LX.
I wonder if any AMD folks could talk about issues relevant to AMD.
FSF -- would be nice to from you.
Anyone at VIA or SiS care to talk?
Intel -- I know you're out there, we'd be happy to see you if
Author: mjones
Date: 2008-02-07 17:09:24 +0100 (Thu, 07 Feb 2008)
New Revision: 576
Modified:
coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
If there is a problem loading VSA we should stop here instead of failing in PCI
scan later.
Signed-off-by: Marc Jones [EMAIL PROTECTED]
Acked-by:
If we want real hardware it is probably going to have to be a cheap via board?
ron
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Carl-Daniel Hailfinger wrote:
- AMD may work out in the next few months... RS690 data sheets (register
reference guide) are publicly available, but SB600 is pretty much secret.
We want to, but I don't know if we will have it done by the summit.
Marc: Any idea whether the process of
On 07.02.2008 08:46, ron minnich wrote:
And it just broke again. Something in phase 6 init is not happening
for some reason.
The cs5536 init is not getting called in phase 6. If somebody wants to
look at the last 30 minutes change log and see what I might have done,
be my guest.
Damn. I
On 06.02.2008 23:23, ron minnich wrote:
On Feb 6, 2008 2:22 PM, Jordan Crouse [EMAIL PROTECTED] wrote:
Unfortunately not. The 8111 chipset on the Serengeti Cheetah is open,
but they aren't available any more in real life. Everything else
is still closed, but hopefully not for ever.
ron minnich wrote:
This code now lets filo find IDE.
but it locks up :-(
oh well. attached.
ron
I preferred the v2 way of doing this. If the AMD IDE device was found it
got initialized. I think it needs a DTS and I think other southbridges
with multiple PCI headers will need this too.
Another missed cc.
On Feb 7, 2008 5:46 PM, Corey Osgood [EMAIL PROTECTED] wrote:
On Feb 7, 2008 5:02 PM, [EMAIL PROTECTED] wrote:
Quoting Marc Karasek [EMAIL PROTECTED]:
Let me add me two cents..
I have dealt with the Intel MACs in the past so let me dreg up some
memorries...
Author: ward
Date: 2008-02-07 23:53:53 +0100 (Thu, 07 Feb 2008)
New Revision: 3096
Modified:
trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb
Log:
Change payload location in 'normal' - this was missed in r3992 and thus breaks
buildrom.
This is a trivial patch.
Signed-off-by: Ward
Author: myles
Date: 2008-02-07 16:54:34 +0100 (Thu, 07 Feb 2008)
New Revision: 108
Modified:
buildrom-devel/config/platforms/Config.in
buildrom-devel/config/platforms/serengeti_cheetah.conf
Log:
Here's the patch to add buildrom support for serengeti_cheetah. It's not
much, because there's
Author: ward
Date: 2008-02-07 22:50:22 +0100 (Thu, 07 Feb 2008)
New Revision: 3094
Modified:
trunk/coreboot-v2/targets/buildtarget
Log:
Make the check for -fno-stack-protector fail silently, if it fails.
This is a trivial patch.
Signed-off-by: Ward Vandewege [EMAIL PROTECTED]
Acked-by: Ward
On 07.02.2008 20:29, Myles Watson wrote:
Coreboot-v3 calls the qemu board qemu-x86, but Coreboot-v2 calls it
qemu-i386. I think that qemu-x86 should be the preferred name.
Does anyone have any reservations about the switch to qemu-x86 in
Coreboot-v2?
Hm. Qemu also has an x86-64 version,
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer myles checked in revision 3093 to
the coreboot source repository and caused the following
changes:
Change Log:
Change references to qemu in Coreboot-v2 calls to qemu-x86.
The patch was followed by
Author: ward
Date: 2008-02-07 23:53:53 +0100 (Thu, 07 Feb 2008)
New Revision: 3096
Modified:
trunk/coreboot-v2/targets/gigabyte/m57sli/Config.lb
Log:
Change payload location in 'normal' - this was missed in r3992 and thus breaks
buildrom.
This is a trivial patch.
Signed-off-by: Ward
The Geode tutorial is also up to date with manual build instructions.
http://www.coreboot.org/AMD_Geode_Porting_Guide#Manual_build
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedprocessors
Update buildrom to pull latest
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer ward checked in revision 3094 to
the coreboot source repository and caused the following
changes:
Change Log:
Make the check for -fno-stack-protector fail silently, if it fails.
This is a trivial
On Feb 7, 2008 12:28 PM, Stefan Reinauer [EMAIL PROTECTED] wrote:
Do we ever want to define devices and compile them in that we don't want
to use?
That's what I can't figure out. I can't recall why that test is there.
ron
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On 08.02.2008 00:34, Marc Jones wrote:
The Geode tutorial is also up to date with manual build instructions.
http://www.coreboot.org/AMD_Geode_Porting_Guide#Manual_build
Marc
Update buildrom to pull latest interrupt free VSA from the AMD website, nrv2b
compress it, pad to 36K it, and append
This patch has LAR create segments for bss.
ron
Fix lar so that it parses .bss section headers.
This is not terribly clean but it works.
Signed-off-by: Ronald G. Minnich [EMAIL PROTECTED]
Index: util/lar/stream.c
===
---
This was easier than I thought :-)
ron
Remove the requirement that all ops have a constructor, since many of them
just use the default.
Signed-off-by: Ronald G. Minnich [EMAIL PROTECTED]
Index: device/device.c
===
---
On 07.02.2008 17:55, ron minnich wrote:
Lar does not currently process bss quite right.
I kind of blame ELF, but see what you think.
Here is filo. These are program headers used in Execution (the 'E' in ELF):
LOAD 0xc0 0x0010 0x0010 0x11430 0x36890 RWE 0x20
LOAD
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer ward checked in revision 3096 to
the coreboot source repository and caused the following
changes:
Change Log:
Change payload location in 'normal' - this was missed in r3992 and thus breaks
buildrom.
On 08.02.2008 00:34, Marc Jones wrote:
The Geode tutorial is also up to date with manual build instructions.
http://www.coreboot.org/AMD_Geode_Porting_Guide#Manual_build
http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.01.bin.gz
is not a gzip compressed file.
You may
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