Ühel kenal päeval, E, 2008-02-18 kell 23:08, kirjutas ron minnich:
> On Feb 18, 2008 11:01 PM, Mart Raudsepp <[EMAIL PROTECTED]> wrote:
>
> > So basically it would be nice if setting up the serial port on DDC pins
> > would be a configurable thing.
>
> configurable each time you boot, or configur
I think the best bet for mainboard guessing is:
1. flashrom should report all matching mainboards
2. flashrom should ALWAYS ask which of the matches to use (even if
there is one!)
That's a simple way to do the guessing that ought to avoid
accidentally writing the wrong image.
ron
--
coreboot ma
On Feb 18, 2008 11:01 PM, Mart Raudsepp <[EMAIL PROTECTED]> wrote:
> So basically it would be nice if setting up the serial port on DDC pins
> would be a configurable thing.
configurable each time you boot, or configurable when you build?
For "each time you boot", could we use CMOS settings?
ro
Ühel kenal päeval, E, 2008-02-18 kell 17:41, kirjutas Marc Jones:
>
> Peter Stuge wrote:
> > On Mon, Feb 18, 2008 at 10:53:07AM -0700, Marc Jones wrote:
> >> The other special thing they do is use the DDC pins on the VGA
> >> connector for serial.
> >
> > Is this their idea or from the 5536?
> >
Ühel kenal päeval, E, 2008-02-18 kell 08:12, kirjutas ron minnich:
> Isn't just about any LX800 board going to put FLASH on the cs5536?
You have three places it can be and the DIVIL_BALL_OPTS MSR registry
needs to match that. If it's wrong, then the writing happens to the
wrong place, which typic
Ühel kenal päeval, E, 2008-02-18 kell 17:07, kirjutas Stefan Reinauer:
> * Mart Raudsepp <[EMAIL PROTECTED]> [080218 14:44]:
> > > Pros:
> > > * can skip boards from PCI based auto-detection logic, requiring
> > > user specifying it;
>
> Why is that a pro? This means there are boards that wi
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "ruik" checked in revision 3108 to
the coreboot source repository and caused the following
changes:
Change Log:
Should be part of changeset 3106.
This patch introduces virtual LDNs changes for W83627EHF
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "ruik" checked in revision 3107 to
the coreboot source repository and caused the following
changes:
Change Log:
Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN
device) an
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "ruik" checked in revision 3106 to
the coreboot source repository and caused the following
changes:
Change Log:
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7
and 9 are
On 18.02.2008 23:55, Marc Jones wrote:
> Carl-Daniel Hailfinger wrote:
>> it seems that executing VSA requires vm86 to be useful. Since we
>> unconditionally execute the VSA, we should unconditionally require vm86
>> support (PCI_OPTION_ROM_RUN_VM86) via Kconfig for Geode targets. Not
>> doing so w
On Mon, Feb 18, 2008 at 07:45:55PM -0500, [EMAIL PROTECTED] wrote:
> > Once you have the base address, you can read the GPIO control
> > registers from /dev/port, with the seek equal to the base address.
>
> How?? This is the part I am looking for, this would be the golden
> ticket:-)
Oh! This ca
Quoting Tom Sylla <[EMAIL PROTECTED]>:
> If you want to look at the GPIOs, from the 82801DB datasheet, it looks
> like you should look at:
>
> 9.1.14 GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)
0x0501
> and
> 9.1.15 GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
> (offsets 58 and 5c in D31:f0, lspc
On Tue, Feb 19, 2008 at 12:18:00AM +0100, Ronald Hoogenboom wrote:
> > > I also noticed that the k8 powernow doesn't work:
> > > 'powernow-k8: MP systems not supported by PSB BIOS structure'
> > > the kernel says.
> >
> > Yeah - I always thought that was related to the lack of ACPI
> > support.
>
Peter Stuge wrote:
> On Mon, Feb 18, 2008 at 10:53:07AM -0700, Marc Jones wrote:
>> The other special thing they do is use the DDC pins on the VGA
>> connector for serial.
>
> Is this their idea or from the 5536?
>
> Anyway, I got the pins for last LinuxTag where I made a cable for
> Stefan. Le
On 19.02.2008 01:21, Peter Stuge wrote:
> On Mon, Feb 18, 2008 at 06:43:05PM +0100, Carl-Daniel Hailfinger wrote:
>
>> A lot of the v3 header files require other header files to be #included
>> before they can be #included. That is completely counter-intuitive. Add
>> necessary #includes to th
Author: hailfinger
Date: 2008-02-19 01:34:32 +0100 (Tue, 19 Feb 2008)
New Revision: 611
Modified:
coreboot-v3/device/smbus_ops.c
coreboot-v3/include/arch/x86/msr.h
coreboot-v3/include/arch/x86/pci_ops.h
coreboot-v3/include/arch/x86/pirq_routing.h
coreboot-v3/include/device/agp.h
Author: hailfinger
Date: 2008-02-19 01:34:32 +0100 (Tue, 19 Feb 2008)
New Revision: 611
Modified:
coreboot-v3/device/smbus_ops.c
coreboot-v3/include/arch/x86/msr.h
coreboot-v3/include/arch/x86/pci_ops.h
coreboot-v3/include/arch/x86/pirq_routing.h
coreboot-v3/include/device/agp.h
On Mon, Feb 18, 2008 at 10:53:07AM -0700, Marc Jones wrote:
> The other special thing they do is use the DDC pins on the VGA
> connector for serial.
Is this their idea or from the 5536?
Anyway, I got the pins for last LinuxTag where I made a cable for
Stefan. Let me know if you need and I'll dig
On 19.02.2008 01:27, Peter Stuge wrote:
> On Mon, Feb 18, 2008 at 09:44:54PM +0100, [EMAIL PROTECTED] wrote:
>
>> Completely replace DBE61 initram code by Alix.1C initram code.
>>
>
>
>> +/* The part is a Hynix hy5du121622ctp-d43.
>>
>
> Still true?
>
This is an unmodified alix1
On Mon, Feb 18, 2008 at 09:44:54PM +0100, [EMAIL PROTECTED] wrote:
> Completely replace DBE61 initram code by Alix.1C initram code.
> +/* The part is a Hynix hy5du121622ctp-d43.
Still true?
//Peter
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboo
On Mon, Feb 18, 2008 at 06:43:05PM +0100, Carl-Daniel Hailfinger wrote:
> A lot of the v3 header files require other header files to be #included
> before they can be #included. That is completely counter-intuitive. Add
> necessary #includes to the header files themselves.
>
> Fix a few cases wh
On Mon, Feb 18, 2008 at 08:12:30AM -0800, ron minnich wrote:
> One other option: have the code see how many boards match based on PCI
> ids. If it is more than one, ask the user which board it is by giving
> them a selection. That way, code won't stop at first match, and it can
> detect ambiguities
r558 had this:
> Author: rminnich
> util/x86emu/vm86.c
> Change uses of dev_find_device to dev_find_pci_device
Unfortunately, x86emu/pcbios/pcibios.c was missed in the conversion. Fix
it to get builds with x86emu compiling again.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Index:
Hi Ward,
On Mon, 2008-02-18 at 17:07 -0500, Ward Vandewege wrote:
> On Mon, Feb 18, 2008 at 11:01:23PM +0100, Ronald Hoogenboom wrote:
> > I also noticed that the k8 powernow doesn't work:
> > 'powernow-k8: MP systems not supported by PSB BIOS structure' the kernel
> > says.
>
> Yeah - I always t
Carl-Daniel Hailfinger wrote:
> Hi,
>
> it seems that executing VSA requires vm86 to be useful. Since we
> unconditionally execute the VSA, we should unconditionally require vm86
> support (PCI_OPTION_ROM_RUN_VM86) via Kconfig for Geode targets. Not
> doing so will either cause compile failures
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi all
I'm attaching the patch which should fix both problems. Fix the undefined u8
type and the bitpos selection in currently unused pnp_read_enable function.
Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Thanks,
Rudolf
-BEGIN PGP SIGNATUR
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "ruik" checked in revision 3105 to
the coreboot source repository and caused the following
changes:
Change Log:
Use virtual LDNs. It enables the GPIOs correctly (it preserves the GPIO5/2 from
a sio_setu
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi,
Thanks,
Yep I fixing that too. Chatting on IRC with the rest of the folks so I got
preempted somehow.
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFH
On Mon, 18 Feb 2008, Ulf Jordan wrote:
On Mon, 18 Feb 2008, Rudolf Marek wrote:
Btw the build is failing with:
srv/svn/linuxbios-extra/tmp/coreboot-v2-3104/src/devices/pnp_device.c:54: error:
`u8' undeclared (first use in this function)
Any idea why it works for me here?
No, but all the fa
On Mon, Feb 18, 2008 at 11:01:23PM +0100, Ronald Hoogenboom wrote:
> I also noticed that the k8 powernow doesn't work:
> 'powernow-k8: MP systems not supported by PSB BIOS structure' the kernel
> says.
Yeah - I always thought that was related to the lack of ACPI support.
> On top of that, the vid
On Mon, 18 Feb 2008, Rudolf Marek wrote:
> Btw the build is failing with:
>
> srv/svn/linuxbios-extra/tmp/coreboot-v2-3104/src/devices/pnp_device.c:54:
> error:
> `u8' undeclared (first use in this function)
>
> Any idea why it works for me here?
No, but all the failed builds are for powerpc tar
On Mon, 2008-02-18 at 21:43 +0100, Carl-Daniel Hailfinger wrote:
> Have you tried vm86 and x86emu? Sometimes only vm86 works due to quirks
> not addressed by the emulator.
>
Can you tell me how to select the vm86 instead of x86emu? Is that v3
only? (I'm using v2!)
> That would be a really big
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Ulf,
> Hmm, shouldn't the last line test the bit at *position* bitpos:
>
> + return !!(tmp & (1 << bitpos));
Yep good catch. I will fix it and I'm sorry about that.
Btw the build is failing with:
srv/svn/linuxbios-extra/tmp/coreboot-v2-310
Finally, now I know it's working (at least the part that I'm patching
here...), here is the patch that uses PIO mode read from SPI rom with
lzma decompression.
This patch allows direct out-of-SPI-flash boot of a Linux kernel. It
circumvents the 512KB limitation in the IT8716f superio of memory
map
On Mon, 18 Feb 2008, [EMAIL PROTECTED] wrote:
> void pnp_set_enable(device_t dev, int enable)
> {
> - pnp_write_config(dev, 0x30, enable?0x1:0x0);
> + u8 tmp, bitpos;
> +
> + tmp = pnp_read_config(dev, 0x30);
> + /* handle the virtual devices, which share same LDN register */
> +
Dear coreboot readers!
This is the automated build check service of coreboot.
The developer "ruik" checked in revision 3104 to
the coreboot source repository and caused the following
changes:
Change Log:
Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, like
mine W83627EH
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi all,
I create this wiki page:
http://www.coreboot.org/SuperIO_port_guide
It contains just a very basic chapter about a virtual LDNs, but I think it
should contain more general stuff. Suggestions?
Rudolf
-BEGIN PGP SIGNATURE-
Version: G
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Thanks,
Committed revision 3107.
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFHue1V3J9wPJqZRNURAiPcAKCZ7ABJE6GuGRkJp5u7ORCkzPJe9ACgxUCT
D7wpta+aI20az8H+t2
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
> We should document the virtual devices somewhere (in the wiki?) so we
> don't forget how it should be done. Especially since there are many
> superios which have the same "problem" but have not been "fixed" yet.
Well we certainly should. Is there so
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Committed revision 3105.
Thanks,
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFHuewz3J9wPJqZRNURAkenAKC5syZXiXJJSXIcROQY1kDSEDXTvACgte+f
/6vfTf6gs3NSiQNbCIJ
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Thanks,
Committed revision 3104.
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFHueuO3J9wPJqZRNURAjKfAKC4eXKgyK3EJwMG1OSiLkc7979RaQCffP8H
SuwFMLV9iIiCwP2F7
On 18.02.2008 21:23, ron minnich wrote:
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
>
> Thanks!
>
Thanks for reviewing! Committed in r610.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreb
Author: hailfinger
Date: 2008-02-18 21:44:54 +0100 (Mon, 18 Feb 2008)
New Revision: 610
Added:
coreboot-v3/mainboard/artecgroup/dbe61/initram.c
Removed:
coreboot-v3/mainboard/artecgroup/dbe61/initram.c
Modified:
coreboot-v3/mainboard/artecgroup/dbe61/Makefile
Log:
Add northbridge/amd/geod
Author: hailfinger
Date: 2008-02-18 21:44:54 +0100 (Mon, 18 Feb 2008)
New Revision: 610
Added:
coreboot-v3/mainboard/artecgroup/dbe61/initram.c
Removed:
coreboot-v3/mainboard/artecgroup/dbe61/initram.c
Modified:
coreboot-v3/mainboard/artecgroup/dbe61/Makefile
Log:
Add northbridge/amd/geod
Author: ruik
Date: 2008-02-18 21:43:09 +0100 (Mon, 18 Feb 2008)
New Revision: 3108
Modified:
trunk/coreboot-v2/util/newconfig/config.g
Log:
Should be part of changeset 3106.
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7
and 9 are
changed, but also a SPI flash
Author: ruik
Date: 2008-02-18 21:43:09 +0100 (Mon, 18 Feb 2008)
New Revision: 3108
Modified:
trunk/coreboot-v2/util/newconfig/config.g
Log:
Should be part of changeset 3106.
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7
and 9 are
changed, but also a SPI flash
On 18.02.2008 21:18, Ronald Hoogenboom wrote:
>>> And there still isn't any VGA output.
>>>
>> :(
>>
>> Can you try a few different graphics cards? My GeForce 6200 cheapo
>> card works well.
>>
>
> I've been able to borrow a cheapo ATI RV515 [Radeon X1300] and that one
> indeed works. S
Author: ruik
Date: 2008-02-18 21:40:02 +0100 (Mon, 18 Feb 2008)
New Revision: 3107
Modified:
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
Log:
Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN
device) and sets the chipset voltage from 1.6V to
Author: ruik
Date: 2008-02-18 21:40:02 +0100 (Mon, 18 Feb 2008)
New Revision: 3107
Modified:
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
Log:
Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN
device) and sets the chipset voltage from 1.6V to
Author: ruik
Date: 2008-02-18 21:37:49 +0100 (Mon, 18 Feb 2008)
New Revision: 3106
Modified:
trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c
trunk/coreboot-v2/src/superio/winbond/w83627ehg/w83627ehg.h
Log:
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LD
Author: ruik
Date: 2008-02-18 21:37:49 +0100 (Mon, 18 Feb 2008)
New Revision: 3106
Modified:
trunk/coreboot-v2/src/superio/winbond/w83627ehg/superio.c
trunk/coreboot-v2/src/superio/winbond/w83627ehg/w83627ehg.h
Log:
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LD
Author: ruik
Date: 2008-02-18 21:35:27 +0100 (Mon, 18 Feb 2008)
New Revision: 3105
Modified:
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
Log:
Use virtual LDNs. It enables the GPIOs correctly (it preserves the GPIO5/2 from
a sio_setup. As side effect I can now
have GAME and MIDI po
Author: ruik
Date: 2008-02-18 21:35:27 +0100 (Mon, 18 Feb 2008)
New Revision: 3105
Modified:
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
Log:
Use virtual LDNs. It enables the GPIOs correctly (it preserves the GPIO5/2 from
a sio_setup. As side effect I can now
have GAME and MIDI po
Author: ruik
Date: 2008-02-18 21:32:46 +0100 (Mon, 18 Feb 2008)
New Revision: 3104
Modified:
trunk/coreboot-v2/src/devices/pnp_device.c
Log:
Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, like
mine W83627EHF.
This patch introduces a concept of virtual LDN. Each virtua
Author: ruik
Date: 2008-02-18 21:32:46 +0100 (Mon, 18 Feb 2008)
New Revision: 3104
Modified:
trunk/coreboot-v2/src/devices/pnp_device.c
Log:
Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, like
mine W83627EHF.
This patch introduces a concept of virtual LDN. Each virtua
On Mon, Feb 18, 2008 at 09:18:12PM +0100, Ronald Hoogenboom wrote:
> > Can you try a few different graphics cards? My GeForce 6200 cheapo
> > card works well.
>
> I've been able to borrow a cheapo ATI RV515 [Radeon X1300] and that one
> indeed works. So what is the story with the Nvidia GeForce 86
Acked-off-by: Ronald G. Minnich <[EMAIL PROTECTED]
Thanks!
ron
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Hi Peter,
> > And there still isn't any VGA output.
>
> :(
>
> Can you try a few different graphics cards? My GeForce 6200 cheapo
> card works well.
I've been able to borrow a cheapo ATI RV515 [Radeon X1300] and that one
indeed works. So what is the story with the Nvidia GeForce 8600GT? Why
doe
On 18.02.2008 18:53, Marc Jones wrote:
> ron minnich wrote:
>
>> On Feb 18, 2008 9:28 AM, Carl-Daniel Hailfinger wrote:
>>
>>
>>> The dbe61 initram code in v3 seems to be in a rather bad shape. Is there
>>> any reason we can't drop it and use the alix1c initram code as template?
>>>
Myles very nicely made all targets use the filename coreboot.rom,
and taught buildrom how to use that filename. Unfortunately, the
Geode platforms didn't get the message. This patch updates the
Geode platforms to use the latest svn revision to take avantage
of Myles fixes.
Jordan
--
Jordan Cro
Quoting ron minnich <[EMAIL PROTECTED]>:
> I think you guys are going in circles :-)
>
> Here is my chance to help :-)
>
> For the last gazillion years the IO ports on the intel parts have been
> about the same. You could probably even reference an old PIIX document
> to see how they are programme
ron minnich wrote:
> On Feb 18, 2008 9:28 AM, Carl-Daniel Hailfinger
> <[EMAIL PROTECTED]> wrote:
>
>
>> The dbe61 initram code in v3 seems to be in a rather bad shape. Is there
>> any reason we can't drop it and use the alix1c initram code as template?
>>
>
> That seems like a reasonable i
A lot of the v3 header files require other header files to be #included
before they can be #included. That is completely counter-intuitive. Add
necessary #includes to the header files themselves.
Fix a few cases where nonexisting files were #included.
Signed-off-by: Carl-Daniel Hailfinger <[EMA
On 18.02.2008 18:19, ron minnich wrote:
> I dropped this idea on Stefan and he tells me I am not insane. I even
> did it BEFORE coffee :-)
>
> Could a LAR contain more LAR files? i.e. could LAR be recursive.
>
Please don't! See the end of the mail for my reasons.
> The recursive nature of LAR
On Feb 18, 2008 9:28 AM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> The dbe61 initram code in v3 seems to be in a rather bad shape. Is there
> any reason we can't drop it and use the alix1c initram code as template?
That seems like a reasonable idea to me.
The alix1c code is pretty flex
On 18.02.2008 18:11, Marc Jones wrote:
> ron minnich wrote:
>
>> I'm going to start on the artec this week as well. Marc, you have one, right?
>>
>>
> Yes, in v2 we never got through the memory settings correct.
>
The dbe61 initram code in v3 seems to be in a rather bad shape. Is the
On 18.02.2008 17:46, Marc Jones wrote:
> Carl-Daniel Hailfinger wrote:
>
>> Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The
>> target does not yet compile due to initram breakage, but the breakage is
>> really old.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTE
On Feb 18, 2008 9:11 AM, Marc Jones <[EMAIL PROTECTED]> wrote:
> Yes, in v2 we never got through the memory settings correct.
OK, does it use SMBUS or not?
I'm ready to go, will set it up on workbench tonight. I am going to
pause alix1c for a bit as it is working so well, it gets a rest as a
rew
Author: hailfinger
Date: 2008-02-18 18:20:47 +0100 (Mon, 18 Feb 2008)
New Revision: 609
Modified:
coreboot-v3/mainboard/artecgroup/dbe61/dts
Log:
Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The
target does not yet compile due to initram breakage, but the breakage is
real
Author: hailfinger
Date: 2008-02-18 18:20:47 +0100 (Mon, 18 Feb 2008)
New Revision: 609
Modified:
coreboot-v3/mainboard/artecgroup/dbe61/dts
Log:
Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The
target does not yet compile due to initram breakage, but the breakage is
real
I dropped this idea on Stefan and he tells me I am not insane. I even
did it BEFORE coffee :-)
Could a LAR contain more LAR files? i.e. could LAR be recursive.
The recursive nature of LAR files could be trivially mirrored in the code.
So, we could have this:
normal/payload.lar
then, the payload
On Feb 18, 2008 12:00 AM, Hamish Guthrie <[EMAIL PROTECTED]> wrote:
> I was the guilty party who created the Eaglelion stuff (quite a long
> time ago), and at that point we were all pretty lax about license headers.
That's for sure. We followed the conventions of the time, wherein a
README at the
ron minnich wrote:
> I'm going to start on the artec this week as well. Marc, you have one, right?
>
> ron
>
>
>
Yes, in v2 we never got through the memory settings correct.
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:[EMAIL PROTECTED]
http://www.amd.com/embeddedp
Hello!
Perfectly.
As others have stated, you have reached the point where you might really
need the board's schematic. Plus a good understanding of the datasheets for
the appropriate part.
I was under the understanding that you had already gotten this far on other
systems.
--
Gregg C Levine [EMAI
I think you guys are going in circles :-)
Here is my chance to help :-)
For the last gazillion years the IO ports on the intel parts have been
about the same. You could probably even reference an old PIIX document
to see how they are programmed. (you'd be surprised how much all the
new stuff look
I'm going to start on the artec this week as well. Marc, you have one, right?
ron
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Carl-Daniel Hailfinger wrote:
> Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The
> target does not yet compile due to initram breakage, but the breakage is
> really old.
>
> Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
>
>
We(I) need to work with Artec on the
Stefan Reinauer wrote:
> Marc Jones wrote:
>> Remove dead Geode defines.
>>
>> Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
>>
>> Index: coreboot-v3/northbridge/amd/geodelx/geodelx.c
>> ===
>> --- coreboot-v3.orig/northbridge/amd/geod
Author: mjones
Date: 2008-02-18 17:37:58 +0100 (Mon, 18 Feb 2008)
New Revision: 608
Modified:
coreboot-v3/northbridge/amd/geodelx/geodelx.c
Log:
Remove dead Geode defines.
Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfing
Author: mjones
Date: 2008-02-18 17:37:58 +0100 (Mon, 18 Feb 2008)
New Revision: 608
Modified:
coreboot-v3/northbridge/amd/geodelx/geodelx.c
Log:
Remove dead Geode defines.
Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfing
On Mon, Feb 18, 2008 at 04:37:59PM +0200, Mart Raudsepp wrote:
>
> Luc Verhaegen pointed out that if subsystem IDs are NULL, then the entry
> already isn't considered in the auto-detection logic.
> I must have misread the logic and assume that even then the first match
> is just picked.
>
> So no
Isn't just about any LX800 board going to put FLASH on the cs5536?
One other option: have the code see how many boards match based on PCI
ids. If it is more than one, ask the user which board it is by giving
them a selection. That way, code won't stop at first match, and it can
detect ambiguities.
* Mart Raudsepp <[EMAIL PROTECTED]> [080218 14:44]:
> > Pros:
> > * can skip boards from PCI based auto-detection logic, requiring
> > user specifying it;
Why is that a pro? This means there are boards that will not work "out
of the box" anymore. That looks like a CON right there.
What's t
If you want to look at the GPIOs, from the 82801DB datasheet, it looks
like you should look at:
9.1.14 GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)
and
9.1.15 GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
(offsets 58 and 5c in D31:f0, lspci -xxx as root is one way to dump)
What value is in those registe
Ühel kenal päeval, E, 2008-02-18 kell 15:44, kirjutas Mart Raudsepp:
> > * Add a field to the struct (either treated as boolean, or a flag),
> > that
> > tells the logic if this entry should be considered in the
> > auto-detection
> > logic or skipped
> > Pros:
> > * can skip boards from PCI
Hello,
Ühel kenal päeval, R, 2008-02-08 kell 17:54, kirjutas Mart Raudsepp:
>
> * Add a field to the struct (either treated as boolean, or a flag),
> that
> tells the logic if this entry should be considered in the
> auto-detection
> logic or skipped
> Pros:
> * can skip boards from PCI bas
Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
> On 18.02.2008 02:45, [EMAIL PROTECTED] wrote:
>> Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
>>
>>> On 16.02.2008 17:57, [EMAIL PROTECTED] wrote:
>>>
Hello,
How do I dump the GPIO I/O Registers in linux. I need to dump the
>
>
> I am talking about CONFIG_PAYLOAD_PREPARSE_ELF, not at all about
> CONFIG_PAYLOAD_NONE.
>
> > > Please don't just remove this code. If you don't like to compile it
> in,
> > > create a config option to disable it. (There is such a config option
> > > already, so I really don't see the gai
Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
> On 18.02.2008 03:25, Peter Stuge wrote:
>> On Sun, Feb 17, 2008 at 09:15:55PM -0500, [EMAIL PROTECTED] wrote:
>>
It can't be probed easily, but perhaps reverse engineered with a
bit of effort.
>>> You mean just probing the GPIO p
Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The
target does not yet compile due to initram breakage, but the breakage is
really old.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Index: LinuxBIOSv3-dbe61/mainboard/artecgroup/dbe61/dts
==
* Rudolf Marek <[EMAIL PROTECTED]> [080217 01:33]:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Hello,
>
> This patch introduces changes for W83627EHF driver. Not only LDN 7 and 9 are
> changed, but also a SPI flash interface which has enable on bit1 and not bit0.
>
> Signed-off-by: Rud
* Rudolf Marek <[EMAIL PROTECTED]> [080217 01:33]:
> -BEGIN PGP SIGNED MESSAGE-
> Attached patch fixes two typos in the sio_setup routine (comment + wrong
> exitLDN
> device) and sets the chipset voltage from 1.6V to 1.5V.
>
> Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Acked-by: Stef
* Rudolf Marek <[EMAIL PROTECTED]> [080217 01:30]:
>
> And finally a patch for my board. It enables the GPIOs correctly (it preserves
> the GPIO5/2 from a sio_setup. As side effect I can now have GAME and MIDI
> ports
> enabled.
>
> It has been tested with my board. It produces same results.
>
* Rudolf Marek <[EMAIL PROTECTED]> [080217 01:24]:
> This patch just modifies the core PNP subsystem, other patches will follow.
>
> Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
On 31.01.2008 00:09, Peter Stuge wrote:
> On Wed, Jan 30, 2008 at 08:40:52AM -0800, ron minnich wrote:
>
>> Possibly this message could be a little less stress-inducing :-)
>>
>
> Yes.
>
> Always print a friendly message when x86emu halts without error.
>
This does not remove the irrita
On 18.02.2008 02:45, [EMAIL PROTECTED] wrote:
> Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
>
>> On 16.02.2008 17:57, [EMAIL PROTECTED] wrote:
>>
>>> Hello,
>>> How do I dump the GPIO I/O Registers in linux. I need to dump the
>>> GPIO's from the southbridge. Anyone?
>>>
>>>
On 18.02.2008 03:25, Peter Stuge wrote:
> On Sun, Feb 17, 2008 at 09:15:55PM -0500, [EMAIL PROTECTED] wrote:
>
>>> It can't be probed easily, but perhaps reverse engineered with a
>>> bit of effort.
>>>
>> You mean just probing the GPIO pins with a meter to find out which
>> ones are asse
I was the guilty party who created the Eaglelion stuff (quite a long
time ago), and at that point we were all pretty lax about license headers.
thanks,
Hamish Guthrie
Jonathan Sturges wrote:
> I've been meaning to contribute a new Geode target I created some months ago
> but never got around t
98 matches
Mail list logo
