Hey Coreboot guys,
I am looking forward to turn an old S939 AMD processor and an Asus A8VE-SE into
a high performance router. To make the power profile fit, I had already
underclocked and undervolted the CPU to 800Mhz with vendor BIOS, with 4x
multiplier and 200Mhz FSB. Any way I change lower
Hi there,
On Thu, Aug 14, 2008 at 03:39:07PM -0600, Ben McClelland wrote:
> I am interested in putting linuxbios on a supermicro H8DCE board
> (http://www.supermicro.com/Aplus/motherboard/Opteron/nForce/H8DCE.cfm).
> Anyone know if this will or will not work for sure? I have been able to
> s
Hi,
I am interested in putting linuxbios on a supermicro H8DCE board
(http://www.supermicro.com/Aplus/motherboard/Opteron/nForce/
H8DCE.cfm). Anyone know if this will or will not work for sure? I
have been able to successfully flash the bios with flashrom, but
haven't tried coreboot yet.
Hello,
On Thu, 2008-08-14 at 13:14 -0400, Warren Togami wrote:
> Could you folks make a new numbered release of mkelfimage? It would
> make things more clear for distributors exactly what version one is
> actually shipping.
IIRC, the version on our repo is the quite same as the one at lnxi, ju
Ward Vandewege wrote:
On Wed, Aug 06, 2008 at 02:55:46PM -0600, Jordan Crouse wrote:
The upstream for mkelfiamge at lnxi has become somewhat unreliable. Reconfigure
buildrom to pull it from our svn tree, where we've had a copy for a while.
Signed-off-by: Ward Vandewege <[EMAIL PROTECTED]>
Acke
Author: rminnich
Date: 2008-08-14 19:00:11 +0200 (Thu, 14 Aug 2008)
New Revision: 765
Modified:
coreboot-v3/northbridge/amd/k8/raminit.c
Log:
Continue cleaning up pci calls in stage1.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modifie
Author: rminnich
Date: 2008-08-14 18:16:07 +0200 (Thu, 14 Aug 2008)
New Revision: 763
Removed:
coreboot-v3/southbridge/nvidia/mcp55/stage1.h
Modified:
coreboot-v3/southbridge/nvidia/mcp55/ide.c
coreboot-v3/southbridge/nvidia/mcp55/lpc.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
c
Jordan Crouse wrote:
>> * fix memory allocator bug that lead to freelist corruption on the first
>> malloc
>> (and spent 8 bytes too much per malloc)
>> * if the memory allocator detects freelist corruption, print a message
>> instead
>> of silently dying.
>>
>
>
>> Signed-off-by: Ste
Author: stepan
Date: 2008-08-14 16:40:10 +0200 (Thu, 14 Aug 2008)
New Revision: 3510
Modified:
trunk/payloads/libpayload/libc/malloc.c
Log:
* fix memory allocator bug that lead to freelist corruption on the first malloc
(and spent 8 bytes too much per malloc)
* if the memory allocator detects
On Thu, Aug 14, 2008 at 11:20:20AM +0200, Arne Georg Gleditsch wrote:
> Marc Jones <[EMAIL PROTECTED]> writes:
> > The log looks good from the CPU side. I didn't look at the diff. When
> > it is ready you should submit it with a signed-off-by.
>
> Yep. I'd like to get some input on the SATA issue
On 14/08/08 13:12 +0200, Stefan Reinauer wrote:
> See patch
>
> --
> coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
> Tel.: +49 761 7668825 • Fax: +49 761 7664613
> Email: [EMAIL PROTECTED] • http://www.coresystems.de/
> Registergericht: Amtsgericht Freiburg • HRB 7656
> Geschä
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: [EMAIL PROTECTED] • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
* fix memor
On 14.08.2008 05:46, ron minnich wrote:
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
>
Thanks, r762.
> Somebody please test.
>
That's a bit difficult unless you already managed to run v3 on real K8
hardware.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
--
coreboot mailing l
Author: hailfinger
Date: 2008-08-14 11:37:46 +0200 (Thu, 14 Aug 2008)
New Revision: 762
Modified:
coreboot-v3/southbridge/nvidia/mcp55/ide.c
coreboot-v3/southbridge/nvidia/mcp55/lpc.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
coreboot-
On 14.08.2008 05:47, ron minnich wrote:
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
>
Thanks, r761.
Regards,
Carl-Daniel
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coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Author: hailfinger
Date: 2008-08-14 11:28:28 +0200 (Thu, 14 Aug 2008)
New Revision: 761
Modified:
coreboot-v3/device/pci_device.c
Log:
Factor out PCI subsystem ID setting. This cleans up the code as well,
arguably fixes some strange behaviour and prepares the code for
per-device subsystem ID se
On 14.08.2008 05:45, ron minnich wrote:
> Plug it in and let's try it out.
>
> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
>
Thanks, r760.
Regards,
Carl-Daniel
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http://www.coreboot.org/mailman/listinfo/coreboot
Author: hailfinger
Date: 2008-08-14 11:25:58 +0200 (Thu, 14 Aug 2008)
New Revision: 760
Modified:
coreboot-v3/arch/x86/stage1.c
coreboot-v3/include/arch/x86/cpu.h
coreboot-v3/include/console.h
coreboot-v3/lib/console.c
Log:
Introduce a generic global variable storage mechanism and swit
On 14.08.2008 05:44, ron minnich wrote:
> Noted at http://www.coreboot.org/Notes_for_v3_ports
>
Thanks!
Regards,
Carl-Daniel
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Marc Jones <[EMAIL PROTECTED]> writes:
> The log looks good from the CPU side. I didn't look at the diff. When
> it is ready you should submit it with a signed-off-by.
Yep. I'd like to get some input on the SATA issues before I do so,
though. If there's anyone with previous experience with the M
Hello,
as is the current status with the CX700 support in coreboot? I wish
the next time coreboot on a Jetway J7F5M1G5E-VHE
(http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=374&proname=J7F5M1G5E-VHE) run. I could, if necessary, such a board in the near future for the development is
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