Re: [coreboot] typo in amdk8/raminit_f.c

Marc Jones schreef: Did you find this on a qrank setup or just visual inspection? You fix looks correct. I found it using vim's quickfix after compiling for m57sli, I guess that's equivalent to visual inspection. I copied the missing pieces from other locations in the same source file until

[coreboot] build service results for r4116

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4116 to the coreboot repository. This caused the following changes: Change Log: r4097 broke the tree and it remains unfixed :-( Repeat: Cosmetic patches shall not break the tree for

[coreboot] [v2] r4116 - in trunk/coreboot-v2/src: cpu/amd/dualcore cpu/amd/quadcore mainboard/amd/serengeti_cheetah mainboard/supermicro/h8dme mainboard/supermicro/h8dmr

Author: stepan Date: 2009-04-15 08:00:01 +0200 (Wed, 15 Apr 2009) New Revision: 4116 Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore_id.c trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/coreboot-v2/sr

[coreboot] flashrom: VIA PC3500G

Patch attached. Might work. Ack if you've tested it. Thanks! //Peter flashrom: Add VIA PC3500G board. It has SPI flash behind ITE8716 on LPC. Signed-off-by: Peter Stuge Index: board_enable.c === --- board_enable.c (revision 4

Re: [coreboot] [v3] r1164 - in coreboot-v3: arch/x86 arch/x86/via mainboard/jetway

On 15.04.2009 00:26, Corey Osgood wrote: > On Tue, Apr 14, 2009 at 6:16 PM, Carl-Daniel Hailfinger < > c-d.hailfinger.devel.2...@gmx.net> wrote: > > >> On 14.04.2009 17:41, s...@coreboot.org wrote: >> >>> Author: cozzie >>> Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) >>> New Revision

Re: [coreboot] CBFS breaks relative payload paths

On Tue, Apr 14, 2009 at 2:49 PM, Richard Smith wrote: > > Without CBFS a payload path like > > payload ../../bios.vx855.090330.bin.elf > > works.  This is nice because I don't lose my binaries everytime I blow away > the work directory and keeps them in a location where copying (or > tarballing) t

Re: [coreboot] [v3] r1164 - in coreboot-v3: arch/x86 arch/x86/via mainboard/jetway

On Tue, Apr 14, 2009 at 6:16 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2...@gmx.net> wrote: > On 14.04.2009 17:41, s...@coreboot.org wrote: > > Author: cozzie > > Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) > > New Revision: 1164 > > > > Modified: > >coreboot-v3/arch/x86/pirq_ro

Re: [coreboot] [v3] r1164 - in coreboot-v3: arch/x86 arch/x86/via mainboard/jetway

On 14.04.2009 17:41, s...@coreboot.org wrote: > Author: cozzie > Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) > New Revision: 1164 > > Modified: >coreboot-v3/arch/x86/pirq_routing.c >coreboot-v3/arch/x86/via/stage0.S >coreboot-v3/mainboard/jetway/Kconfig > Log: > Enable caching fo

[coreboot] CBFS breaks relative payload paths

Without CBFS a payload path like payload ../../bios.vx855.090330.bin.elf works. This is nice because I don't lose my binaries everytime I blow away the work directory and keeps them in a location where copying (or tarballing) the trees around keeps the images with them. If you try to build

[coreboot] build service results for r4115

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 4115 to the coreboot repository. This caused the following changes: Change Log: EPIA-CN does not have any ACPI tables. Fixes manual and auto build here. Signed-off-by: Peter Stuge

Re: [coreboot] build service results for r4114

coreboot information wrote: > Compilation of via:epia-cn is still broken > See the error log at > http://qa.coreboot.org/log_buildbrd.php?revision=4114&device=epia-cn&vendor=via&num=2 qa says: make[1]: *** No rule to make target `coreboot-v2-4114//src/mainboard/via/epia-cn/acpi_tables.c', needed

[coreboot] [v2] r4115 - trunk/coreboot-v2/src/mainboard/via/epia-cn

Author: stuge Date: 2009-04-14 22:51:41 +0200 (Tue, 14 Apr 2009) New Revision: 4115 Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb Log: EPIA-CN does not have any ACPI tables. Fixes manual and auto build here. Signed-off-by: Peter Stuge Acked-by: Peter Stuge Modified: trun

[coreboot] build service results for r4114

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 4114 to the coreboot repository. This caused the following changes: Change Log: util/cbfstool/tools/rom-mk*->cbfs-mk* rename Signed-off-by: Peter Stuge Acked-by: Ronald G. Minnich

Re: [coreboot] Seabios configuration

Kevin O'Connor wrote: > Well, it took a while, but I finally updated the wiki: > > http://www.coreboot.org/SeaBIOS I just made the romfs->cbfs change there. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] SeaBIOS and CBFS with payloads

Kevin O'Connor wrote: > rom-mkpayload < myprog.elf > myprog.pay > romtool somedir/bios.bin add myprog.pay img/myprog 0x20 > romtool somedir/bios.bin print Just a note that these commands are now cbfs-mkpayload and cbfstool, respectively. //Peter -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] util/cbfstool/tools/rom-mk*->cbfs-mk* rename

ron minnich wrote: > Acked-by: Ronald G. Minnich Thanks! r4114 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [v2] r4114 - in trunk/coreboot-v2/util/cbfstool: . tools

Author: stuge Date: 2009-04-14 21:48:32 +0200 (Tue, 14 Apr 2009) New Revision: 4114 Added: trunk/coreboot-v2/util/cbfstool/tools/cbfs-mkpayload.c trunk/coreboot-v2/util/cbfstool/tools/cbfs-mkstage.c Removed: trunk/coreboot-v2/util/cbfstool/tools/rom-mkpayload.c trunk/coreboot-v2/util/c

[coreboot] cbfs wiki page up

Since several people in IRC have already gone looking for it Just Jordan's email cleaned up a little for wiki. Please add/edit etc. http://www.coreboot.org/CBFS Marc -- http://marcjonesconsulting.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/

Re: [coreboot] typo in amdk8/raminit_f.c

On Mon, Apr 13, 2009 at 9:12 AM, Ronald Hoogenboom wrote: > Hi, > > There is a typo in amdk8/raminit_f.c regarding the preprocessor symbol > QRANK_DIMM_SUPPORT in line 2208, which caused the protected code > fragment never to be included for compilation. > I guessed what the dimm_mask and sz.rank

Re: [coreboot] [PATCH] [v3] Fix ROM caching on Via C7

On Tue, Apr 14, 2009 at 9:56 AM, Corey Osgood wrote: > On Tue, Jan 6, 2009 at 12:31 PM, Marc Jones wrote: >> >> On Tue, Jan 6, 2009 at 7:39 AM, Myles Watson wrote: >> > On Tue, Jan 6, 2009 at 4:52 AM, Corey Osgood >> > wrote: >> >> Tested and working on hardware :D >> > >> > Great job! >> > >>

Re: [coreboot] [PATCH] [v3] Fix ROM caching on Via C7

On Tue, Jan 6, 2009 at 12:31 PM, Marc Jones wrote: > On Tue, Jan 6, 2009 at 7:39 AM, Myles Watson wrote: > > On Tue, Jan 6, 2009 at 4:52 AM, Corey Osgood > wrote: > >> Tested and working on hardware :D > > > > Great job! > > > > As I read your patch I wondered if there's a good reason to disabl

Re: [coreboot] [PATCH] flush CPU queue when PE set 0

On Mon, Apr 13, 2009 at 5:42 PM, Peter Stuge wrote: > Rudolf Marek wrote: >> The trick is to use 0x66 prefix (done with ljmpl) it will allow to >> jump in real mode to any EIP addresses ;) > > Yep, this is needed. Ah, the pmode and DOS32 days. > > >> Signed-off-by: Rudolf Marek > > Acked-by: Pete

[coreboot] [v3] r1164 - in coreboot-v3: arch/x86 arch/x86/via mainboard/jetway

Author: cozzie Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) New Revision: 1164 Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/arch/x86/via/stage0.S coreboot-v3/mainboard/jetway/Kconfig Log: Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware a

Re: [coreboot] SeaBIOS HAVE_HIGH_TABLES

On Tue, Apr 14, 2009 at 11:37 PM, Jason Wang wrote: > On Tue, Apr 14, 2009 at 8:13 PM, Joseph Smith wrote: >> >> Hello, >> I was just checking out the SeaBIOS Wiki page updates (great job by the >> way:-)). I am wondering about the HAVE_HIGH_TABLES section. It seems so say >> to statically add yo

Re: [coreboot] [PATCH] VIA CX700 support

On Tue, Apr 14, 2009 at 5:51 AM, Peter Stuge wrote: > Stephan Raue wrote: > >> If they are using the same superio you could try simply booting a > >> coreboot image built for the VIA board on the Jetway board > > > > here is the first problem - Jetway seems like to use Fintek > > SuperIOs now Cor

Re: [coreboot] v2/src romfs->cbfs rename

On Tue, Apr 14, 2009 at 4:03 AM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2...@gmx.net> wrote: > On 14.04.2009 03:29, Richard Smith wrote: > > Peter Stuge wrote: > >> ron minnich wrote: > >>> did you test with abuild :-) > >> > >> No sir. I have neither procedure nor CPU power for abuild. :\

Re: [coreboot] util/cbfstool/tools/rom-mk*->cbfs-mk* rename

Acked-by: Ronald G. Minnich -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset

On Tue, 14 Apr 2009 08:56:06 -0500, bari wrote: > Mansoor wrote: >> Hi, >> >> I have a Atom Silverthorne Poulsbo based board >> (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this >> platform. >> >> I would like to know if anybody has started/suceeded in porting coreboot >

Re: [coreboot] yabel: romfs->cbfs rename

On Tue, Apr 14, 2009 at 10:24 AM, Peter Stuge wrote: > Pattrick Hueper wrote: >> that definition seems to be leftover from the porting efforts... >> it was for another romfs though... > > Ok! That was my guess from dates and so on. > > >> since its not used in yabel anywhere currently... i would s

[coreboot] [v3] r1163 - coreboot-v3/util/x86emu/yabel/compat

Author: phueper Date: 2009-04-14 15:58:45 +0200 (Tue, 14 Apr 2009) New Revision: 1163 Modified: coreboot-v3/util/x86emu/yabel/compat/of.h Log: remove unnecessary function definition Signed-off-by: Pattrick Hueper Acked-by: Peter Stuge Modified: coreboot-v3/util/x86emu/yabel/compat/of.h

Re: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset

Mansoor wrote: Hi, I have a Atom Silverthorne Poulsbo based board (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this platform. I would like to know if anybody has started/suceeded in porting coreboot to Atom, also if there is anyone interested in such a port. There

[coreboot] SeaBIOS HAVE_HIGH_TABLES

Hello, I was just checking out the SeaBIOS Wiki page updates (great job by the way:-)). I am wondering about the HAVE_HIGH_TABLES section. It seems so say to statically add you memory size (uint64_t high_tables_base = ( )*1024*1024 - (64*1024); where is the amount of memory (in MiB) available o

[coreboot] util/cbfstool/tools/rom-mk*->cbfs-mk* rename

cbfstool and tools/cbfs-mk* builds with this change. //Peter util/cbfstool/tools/rom-mk*->cbfs-mk* rename Signed-off-by: Peter Stuge Index: util/cbfstool/tools/rom-mkstage.c === --- util/cbfstool/tools/rom-mkstage.c (revision 41

Re: [coreboot] [PATCH] VIA CX700 support

Stephan Raue wrote: >> If they are using the same superio you could try simply booting a >> coreboot image built for the VIA board on the Jetway board > > here is the first problem - Jetway seems like to use Fintek > SuperIOs now Coreboot has included F71805F/FG and the J7F5M1G5E > Board uses F7180

Re: [coreboot] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset

Hello Mansoor, welcome to the coreboot community! Mansoor wrote: > I have a Atom Silverthorne Poulsbo based board > (http://www.iwavesystems.com/iW-Q7.htm). > I want to port coreboot on this platform. That's wonderful! > I would like to know if anybody has started/suceeded in porting > coreb

Re: [coreboot] yabel: romfs->cbfs rename

Pattrick Hueper wrote: > that definition seems to be leftover from the porting efforts... > it was for another romfs though... Ok! That was my guess from dates and so on. > since its not used in yabel anywhere currently... i would say we > can remove the line altogether... Great. Thanks for loo

Re: [coreboot] More ways to run central abuild

Carl-Daniel Hailfinger wrote: > Security reasons? What's stopping anyone from mailing a patch which > starts a shell on the abuild server which listens on port 12345 or > similar fun? Maybe use a PGP signature? That presents new problems, but the basic idea is still fantastic - making testing eve

Re: [coreboot] v2/src romfs->cbfs rename

Stefan Reinauer wrote: > >> did you test with abuild :-) > > > > No sir. I have neither procedure nor CPU power for abuild. :\ > > Please make yourself familiar with the coreboot procedure, then: > http://www.coreboot.org/Development_Guidelines It says "please run before commit" but not much more

Re: [coreboot] v2/src romfs->cbfs rename

On 14.04.2009 03:29, Richard Smith wrote: > Peter Stuge wrote: >> ron minnich wrote: >>> did you test with abuild :-) >> >> No sir. I have neither procedure nor CPU power for abuild. :\ >> >> By the time I would have managed to run abuild once, the server would >> probably have run abuild thrice, i

[coreboot] build service results for r4113

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 4113 to the coreboot repository. This caused the following changes: Change Log: v2/src romfs->cbfs rename This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.

Re: [coreboot] yabel: romfs->cbfs rename

Hi, that definition seems to be leftover from the porting efforts... it was for another romfs though... since its not used in yabel anywhere currently... i would say we can remove the line altogether... diff --git a/util/x86emu/yabel/compat/of.h b/util/x86emu/yabel/compat/of.h index aced2d5..907

Re: [coreboot] v2/src romfs->cbfs rename

ron minnich wrote: > Acked-by: Ronald G. Minnich > > abuild tested. There are one or two fails but none related to this > patch. Wow - thanks! r4113 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] v2/src romfs->cbfs rename

On 14.04.2009 3:06 Uhr, Peter Stuge wrote: > ron minnich wrote: > >> did you test with abuild :-) >> > > No sir. I have neither procedure nor CPU power for abuild. :\ > Please make yourself familiar with the coreboot procedure, then: http://www.coreboot.org/Development_Guidelines It oft

Re: [coreboot] [PATCH] VIA CX700 support

Am 13.04.2009 06:40, schrieb Peter Stuge: Hi Stephan, Stephan Raue wrote: how i can add support for Jetway J7F5M1G5E-VHE-LF (http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=374&proname=J7F5M1G5E-VHE-LF) in coreboot with this patch, Start by comparing the added board (VIA ref

[coreboot] build service results for r4112

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4112 to the coreboot repository. This caused the following changes: Change Log: fix up the tree. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Build Log: Compilatio