Author: hailfinger
Date: 2009-05-04 14:18:10 +0200 (Mon, 04 May 2009)
New Revision: 454
Modified:
trunk/Makefile
trunk/flashrom.c
Log:
flashrom 0.9.0
Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Peter Stuge
Modified: trunk/Makefile
Author: hailfinger
Date: 2009-05-04 14:22:27 +0200 (Mon, 04 May 2009)
New Revision: 455
Added:
tags/
Log:
Create a tags directory for flashrom.
Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Carl-Daniel Hailfinger
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Author: hailfinger
Date: 2009-05-04 14:23:25 +0200 (Mon, 04 May 2009)
New Revision: 456
Added:
tags/flashrom-0.9.0/
Log:
flashrom 0.9.0 tag
Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Peter Stuge
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Author: hailfinger
Date: 2009-05-04 14:29:59 +0200 (Mon, 04 May 2009)
New Revision: 457
Modified:
trunk/Makefile
Log:
Onwards with development. Re-add the svn revision to the version string.
Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Carl-Daniel Hailfinger
Modified: trunk/Makefile
===
The flashrom developers are happy to announce the release of flashrom 0.9.0.
flashrom is a utility for reading, writing, erasing and verifying flash
ROM chips.
flashrom is often used to flash BIOS/coreboot/firmware images because it
allows you to update your BIOS/coreboot/firmware without opening
#130: flashrom segfault (with backtrace)
-+--
Reporter: frag...@… | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone:
On Fri, May 01, 2009 at 11:42:17PM +0200, Rudolf Marek wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Hi again,
>
> I'm attaching a rewritten version from VGA ROM, which mimics the BIOS init.
>
> Sadly enough it is still not hitting the all required regs to make powernow
> working
Hrm. This is the AR register accesses. They require a read from STAT1
for the internal counter to be reset and thus for correct read/write
operations.
I inserted a delay there, now it works. The bios has there just some
CALL and I have it in one instruction stream. Maybe it is too fast.
#130: flashrom segfault (with backtrace)
-+--
Reporter: frag...@… | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone:
This patch removes these warnings:
Makefile:435: warning: overriding commands for target `src/lib/memset.o'
And replaces these debug messages:
partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8>
part pci_domain
with:
partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part
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Hash: SHA1
Hello all,
I decided to speak a bit about coreboot in a student (university) UNIX/Linux
club. Are there any slides so I can "pirate" them and maybe improve them a bit?
Thanks,
Rudolf
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Version: GnuPG v1.4.9 (GNU/Linux)
Com
Author: ruik
Date: 2009-05-04 21:26:43 +0200 (Mon, 04 May 2009)
New Revision: 4252
Modified:
trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
Log:
The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles
reverted this change.
I think we can return the 4099 back under HAVE_AC
#131: New flashrom motherboard support
-+--
Reporter: anonymous | Owner: somebody
Type: enhancement| Status: new
Priority: trivial| Miles
On Mon, May 4, 2009 at 1:26 PM, wrote:
> Author: ruik
> Date: 2009-05-04 21:26:43 +0200 (Mon, 04 May 2009)
> New Revision: 4252
>
> Modified:
> trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c
> Log:
> The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles
> reverted this
> +
> +#if HAVE_ACPI_RESUME == 1
> + /* clear only coreboot used region of memory. Note: this may break
> ECC enabled boards */
> + clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE -
> DCACHE_RAM_SIZE);
> +#else
> clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCA
Wonderful.
Acked-by: Ronald G. Minnich
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Author: myles
Date: 2009-05-04 22:27:09 +0200 (Mon, 04 May 2009)
New Revision: 4253
Modified:
trunk/coreboot-v2/util/newconfig/config.g
Log:
This patch removes these warnings:
Makefile:435: warning: overriding commands for target `src/lib/memset.o'
And replaces these debug messages:
partobj di
On Mon, May 4, 2009 at 2:08 PM, ron minnich wrote:
> Wonderful.
Thanks.
> Acked-by: Ronald G. Minnich
Rev 4253.
Myles
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On Sun, May 3, 2009 at 1:42 AM, Patrick Georgi wrote:
> Am 03.05.2009 02:40, schrieb Ward Vandewege:
>>
>> On Sat, May 02, 2009 at 04:38:12PM -0700, ron minnich wrote:
>>>
>>> On Sat, May 2, 2009 at 2:58 PM, Ward Vandewege wrote:
On Sat, May 02, 2009 at 01:42:34PM -0700, ron minnich wro
On Mon, 4 May 2009, Carl-Daniel Hailfinger wrote:
The flashrom developers are happy to announce the release of flashrom 0.9.0.
Downloaded http://qa.coreboot.org/releases/flashrom-0.9.0.tar.bz2
compiles with gcc-4.4.0
installs, runs.
Good Job!
Russ
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> I will leave it to you to fill in the blanks. Please, no #ifdef around
> this very important piece of code. Let's not put in changes that we
> *know* will break boards :-)
Hmm I dont have an ECC board. So maybe Myles could test. Second reason is tha
On Mon, May 4, 2009 at 2:41 PM, Rudolf Marek wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
>> I will leave it to you to fill in the blanks. Please, no #ifdef around
>> this very important piece of code. Let's not put in changes that we
>> *know* will break boards :-)
>
> Hmm I dont ha
On Mon, May 4, 2009 at 1:41 PM, Rudolf Marek wrote:
> Hmm I dont have an ECC board. So maybe Myles could test. Second reason is
> that I
> prefer to have here the ifdef because the RESUME stuff is quite unmature but
> works at least somehow. I'm willing to test the changes when we know it works
Author: stuge
Date: 2009-05-04 23:03:59 +0200 (Mon, 04 May 2009)
New Revision: 458
Modified:
trunk/flashchips.c
Log:
SST25VF080B TEST_OK_READ
Per report from from Henning Fleddermann. Thanks!
Signed-off-by: Peter Stuge
Acked-by: Peter Stuge
Modified: trunk/flashchips.c
===
Author: hailfinger
Date: 2009-05-05 00:33:50 +0200 (Tue, 05 May 2009)
New Revision: 459
Modified:
trunk/chipset_enable.c
Log:
Force enabling SPI mode for SB600 is a bad idea and leads to hangs.
Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we
boot via SPI ROM.
The code to
On 02.02.2009 05:12, Bao, Zheng wrote:
> Signed-off-by: Zheng Bao
>
> This patch is about flashrom running on dbm690t. It was sent several
> months ago and hasn't got any response yet. Now it deals with 3
> problems.
> 1. Fix the bug that the flashrom would hang if there is not SPI chip. A
> timeo
Attached. This patch lets us create XIP stages for cbfs.
ron
This patch adds cbfs support for XIP stages. An XIP stage is code in
ROM that is not copied anywhere; is is eXecuted In Place.
Such support is necessary if we are to have ROM code that is visible in
cbfs. This change will also, over
> Attached. This patch lets us create XIP stages for cbfs.
I'd like to see the picture of what you're imagining here. I thought CBFS
was designed to grow in only one direction. Are you going to have to add
components in a certain order to make this work? I don't see where you're
padding or ins
I no longer have a setup for Fam10 so someone will need to test this
patch. This doesn't include new errata for C2 (which really needs to
be addressed).
Update equivalent processor revision ID to load latest microcode
patches and register setting for all FAM10 processors.
This does not include new
On Mon, May 4, 2009 at 12:49 PM, Rudolf Marek wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> Hello all,
>
> I decided to speak a bit about coreboot in a student (university) UNIX/Linux
> club. Are there any slides so I can "pirate" them and maybe improve them a
> bit?
>
> Thanks,
>
On Mon, May 4, 2009 at 8:55 PM, Myles Watson wrote:
>
>> Attached. This patch lets us create XIP stages for cbfs.
>
> I'd like to see the picture of what you're imagining here. I thought CBFS
> was designed to grow in only one direction. Are you going to have to add
> components in a certain ord
I will test this configuration via SimNow, further improve if issues
arise.
Acked-by: Vincent Lim (vincent@amd.com)
Best Regards,
Vincent Lim
SimNow Team
Performance CoE
Central Engineering
T 512.602.1618
F 512.602.7745
-Original Message-
From: Marc Jones [mailto:marcj...@gmail.c
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