On 14.05.2009 04:23, Peter Stuge wrote:
> Carl-Daniel Hailfinger wrote:
>
>> +@echo -n $(SVNVERSION) >flashrom-$(VERSION)/.svnversion
>>
>
> That's pretty ugly.
>
It's the only way I saw to preserve the svn revision in the tarball
(well except $Rev$ which would have been sprinkled o
Am 14.05.2009 00:01, schrieb Myles Watson:
tables.diff:
Add comments.
Remove ACPI-specific code.
Align low_table_end after gdt (so it matches high_table_end).
Correct "New low_table_end..." line in coreboot_table.c.
high_low.diff:
Factor out common code for writing tables.
both.diff:
If we need
Hi there,
as coreboot gives us the possibility to fully control a board's boot
process, I would like to suggest to make a small end-user project.
As I do want to build some web and application servers using xen. I
think about joining forces and build a reference-implementation for that.
So anyo
Am 14.05.2009 10:44, schrieb Ludwig Jaffe:
The Server just boots coreboot and then the xen-kernel with the
essential tools. So if anything goes wrong (Misconfigured Xen-clients,
hdd-failures, Network, other pain which does not affect cpu+chipset)
the box will be able to be put to life again from
Ludwig Jaffe wrote:
> Within coreboot, using a 8MByte Bios we should have enough space
> for the userland.
Note that 8Mbyte flash chips are very rare. Flash chip sizes are
always expressed in bits, so 8MB means 8Mbit, ie. 1Mbyte.
> Now the question is, which board/chipset would you choose?
Prob
On Tue, May 12, 2009 at 01:18:35PM +0200, Rudolf Marek wrote:
> Hello,
>
> I'm about to order some DIP8 SPI flashes size 1MB. If someone is from
> europe I think I can send them just like a normal letter.
>
> Farnell wants 5EUR for postage, but I have in plan to use some local
> distributor so
Author: raijin
Date: Thu May 14 08:11:23 EDT 2009
Modified: trunk/flashrom/cbtables.c
Log: Spelling Error in comment
Signed-off-by: Daniel McLellan
--- cbtable.c~ 2009-05-13 12:38:10.093503294 -0400
+++ cbtable.c 2009-05-13 12:38:10.216503075 -0400
@@ -101,9 +101,9 @@
stru
On Mon, May 11, 2009 at 06:18:47PM +0200, Carl-Daniel Hailfinger wrote:
> Add a dummy SPI controller driver, similar to the dummy LPC/FWH/Parallel
> flasher driver.
> Does not support reading or writing the fake chip yet.
>
> flashrom --programmer dummy
> also enables the dummy SPI controller driv
Luc Verhaegen wrote:
> > Is someone interrested?
>
> If the M2V takes 1MB, then i'll take 2.
Should work just fine.
//Peter
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Author: stuge
Date: 2009-05-14 14:41:00 +0200 (Thu, 14 May 2009)
New Revision: 506
Modified:
trunk/cbtable.c
Log:
Fix spelling error in comment
Author: raijin
Signed-off-by: Daniel McLellan
Acked-by: Peter Stuge
Modified: trunk/cbtable.c
===
psibyrion wrote:
> Log: Spelling Error in comment
>
> Signed-off-by: Daniel McLellan
Thanks, r506.
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Author: hailfinger
Date: 2009-05-14 14:59:36 +0200 (Thu, 14 May 2009)
New Revision: 507
Modified:
trunk/dummyflasher.c
trunk/flash.h
trunk/spi.c
Log:
Add a dummy SPI controller driver, similar to the dummy LPC/FWH/Parallel
flasher driver.
Does not support reading or writing the fake chip
On 14.05.2009 14:31, Uwe Hermann wrote:
> On Mon, May 11, 2009 at 06:18:47PM +0200, Carl-Daniel Hailfinger wrote:
>
>> Add a dummy SPI controller driver, similar to the dummy LPC/FWH/Parallel
>> flasher driver.
>> Does not support reading or writing the fake chip yet.
>>
>> flashrom --programmer
On Wed, May 13, 2009 at 11:23:52PM -0400, Ward Vandewege wrote:
> > which is correct (the last two digits are 00).
>
> Huh:
>
> $ v ../payloads/sgabios.bin
> -rwxr-xr-x 1 root src 3169 2009-04-29 13:56 ../payloads/sgabios.bin*
> $ tools/checksum.py <../payloads/sgabios.bin
> sum=50b76
Heh - sg
Before I apply this patch, I'd like to see a test on a non-Linux OS.
On 12.05.2009 19:17, Christian Ruppert wrote:
> Signed-off-by: Christian Ruppert
>
> Index: Makefile
> ===
> --- Makefile (revision 483)
> +++ Makefile (working c
Hi Nathan,
there was some discussion on the coreboot mailing list, and it seems
that the SGABIOS binary doesn't have a checksum calculated for it,
which means that some BIOSes refuse to initialize it.
The SeaBIOS project maintained by Kevin has a utility for calculating
checksums, available at:
> -Original Message-
> From: coreboot-bounces+mylesgw=gmail@coreboot.org [mailto:coreboot-
> bounces+mylesgw=gmail@coreboot.org] On Behalf Of Bao, Zheng
> Sent: Thursday, May 14, 2009 12:14 AM
> To: coreboot
> Subject: Re: [coreboot] [PATCH] Table code cleanup
>
> I tried tables.d
On Wed, May 13, 2009 at 10:26 PM, Peter Stuge wrote:
> If MMCONFIG is the term that applies, then better use that instead:
>
> MMCONFIG_BAR_BASE and _SIZE
One note, "BAR" might be a little bit confusing. "BAR" has a pretty
strong tie to an actual register in a PCI config header. I think the
varia
Tom Sylla wrote:
> > MMCONFIG_BAR_BASE and _SIZE
>
> One note, "BAR" might be a little bit confusing. "BAR" has a pretty
> strong tie to an actual register in a PCI config header.
Yes.
> I think the variables you are describing are really just "the
> address and size where MMCONFIG is located",
> -Original Message-
> From: Patrick Georgi [mailto:patr...@georgi-clan.de]
> Sent: Thursday, May 14, 2009 2:00 AM
> To: Myles Watson
> Cc: coreboot
> Subject: Re: [coreboot] [PATCH] Table code cleanup
>
> Am 14.05.2009 00:01, schrieb Myles Watson:
> > tables.diff:
> > Add comments.
> >
On 14.05.2009 16:03, Peter Stuge wrote:
> Tom Sylla wrote:
>
>> MMCONFIG_BASE and MMCONFIG_SIZE
>>
>> seem pretty clear and simple
>>
>
> Makes perfect sense. I want that.
>
Fully agreed.
Tom, thanks for coming up with that name.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Author: hailfinger
Date: 2009-05-14 16:17:07 +0200 (Thu, 14 May 2009)
New Revision: 508
Modified:
trunk/Makefile
Log:
Improve makefile structure a bit.
Signed-off-by: Christian Ruppert
Acked-by: Carl-Daniel Hailfinger
Modified: trunk/Makefile
===
On 14.05.2009 15:36, Carl-Daniel Hailfinger wrote:
> On 12.05.2009 19:17, Christian Ruppert wrote:
>
>> Signed-off-by: Christian Ruppert
> Before I apply this patch, I'd like to see a test on a non-Linux OS.
>
> It should be possible to change .test.c compilation a bit to
> automatically det
Author: uwe
Date: 2009-05-14 16:51:14 +0200 (Thu, 14 May 2009)
New Revision: 509
Modified:
trunk/Makefile
Log:
Cosmetics and eliminate unneeded vars as per IRC discussion (trivial).
Build-tested and 'make PREFIX=/tmp/foo install' tested by me.
Signed-off-by: Uwe Hermann
Acked-by: Uwe Hermann
Carl-Daniel Hailfinger wrote:
> Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
> should handle such special opcode failure gracefully on ICH and
> compatible chipsets.
Acked-by: FENG Yu Ning
iirc, Rudolf came to similar solution before, and I tried to hold it
back. That
Am 14.05.2009 16:04, schrieb Myles Watson:
+ smp_write_floating_table_physaddr(low_table_end, mpc_start);
crashes some linux versions that expect the MP table to directly follow
the floating table, I think.
? I must have misunderstood. How can we put MP table in the high tables
area if
Hi Peter,
There is an tools[1] which can calculate the checksum. I am not sure if
it can help,
really hope it can help
[1]http://vps.dorilex.net/pub/scm/usbrom.git
On Thu, May 14, 2009 at 9:38 PM, Peter Stuge wrote:
> Hi Nathan,
>
> there was some discussion on the coreboot mailing list, and
> -Original Message-
> From: Patrick Georgi [mailto:patr...@georgi-clan.de]
> Sent: Thursday, May 14, 2009 9:15 AM
> To: Myles Watson
> Cc: 'coreboot'
> Subject: Re: [coreboot] [PATCH] Table code cleanup
>
> Am 14.05.2009 16:04, schrieb Myles Watson:
> >> + smp_write_floating_table_phys
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Add missing GPL headers to two files.
Signed-off-by: Uwe Hermann
Index: coreboot_tables.h
==
#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E)
-+--
Reporter: j...@… | Owner: somebody
Type: defect | Status: new
Priority: major
#135: Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E)
-+--
Reporter: j...@… | Owner: somebody
Type: defect | Status: new
Priority: major
Robert,
Is there anything specific that I need to know with respect to where
the Multiboot table ends up? If you could give me memory ranges that
are acceptable, that would be great. Should it be in the high tables
area as well?
Thanks,
Myles
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ht
On Thu, May 14, 2009 at 9:33 AM, Myles Watson wrote:
>
>
>> -Original Message-
>> From: Patrick Georgi [mailto:patr...@georgi-clan.de]
>> Sent: Thursday, May 14, 2009 9:15 AM
>> To: Myles Watson
>> Cc: 'coreboot'
>> Subject: Re: [coreboot] [PATCH] Table code cleanup
>>
>> Am 14.05.2009 16:
On Wed, 13 May 2009 09:40:27 -0400, Joseph Smith
wrote:
>
>
>
> On Wed, 13 May 2009 00:01:58 -0400, Joseph Smith
> wrote:
>>
>>
>>
>> On Wed, 13 May 2009 05:07:25 +0200, coreboot information
>> wrote:
>>> Dear coreboot readers!
>>>
>>> This is the automatic build system of coreboot.
>>>
>>
Am 14.05.2009 18:46, schrieb Myles Watson:
On Thu, May 14, 2009 at 9:33 AM, Myles Watson wrote:
Sorry to be dense. Could we do this in terms of which tables we want in
each place?
Page0 (low_table_start):
COREBOOT TABLE
0xf (rom_table):
PIRQ
MPTABLE (with floating table)
ACPI bulk
0x7ff
> -Original Message-
> From: Patrick Georgi [mailto:patr...@georgi-clan.de]
> Sent: Thursday, May 14, 2009 11:13 AM
> To: Myles Watson
> Cc: coreboot
> Subject: Re: [coreboot] [PATCH] Table code cleanup
>
> Am 14.05.2009 18:46, schrieb Myles Watson:
> > On Thu, May 14, 2009 at 9:33 AM, M
Hey,
here is the first official patch to support a user specified NIC via pci id
(bus:slot:func).
example: flashrom -p nic3com=xx:xx.x
Signed-off-by: Christian Ruppert
Regards,
Christian Ruppert
Index: flash.h
===
--- flash.h (re
On Thu, May 14, 2009 at 10:17:48AM -0600, Myles Watson wrote:
> Robert,
>
> Is there anything specific that I need to know with respect to where
> the Multiboot table ends up? If you could give me memory ranges that
> are acceptable, that would be great. Should it be in the high tables
> area as
#136: failed to boot under KVM\QEMU
-+--
Reporter: silic...@… | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone:
> -Original Message-
> From: Patrick Georgi [mailto:patr...@georgi-clan.de]
> Sent: Thursday, May 14, 2009 11:13 AM
> To: Myles Watson
> Cc: coreboot
> Subject: Re: [coreboot] [PATCH] Table code cleanup
>
> Am 14.05.2009 18:46, schrieb Myles Watson:
> > On Thu, May 14, 2009 at 9:33 AM, M
Author: uwe
Date: 2009-05-14 20:57:26 +0200 (Thu, 14 May 2009)
New Revision: 510
Modified:
trunk/flash.h
trunk/flashrom.c
trunk/internal.c
trunk/nic3com.c
Log:
3COM: Add support for users to specify a certain NIC via PCI bus:slot.func
notation, in case there are multiple NICs in one sy
On Thu, May 14, 2009 at 08:11:35PM +0200, Christian Ruppert wrote:
> Hey,
>
> here is the first official patch to support a user specified NIC via pci id
> (bus:slot:func).
> example: flashrom -p nic3com=xx:xx.x
>
> Signed-off-by: Christian Ruppert
Thanks, committed in r510 with a few changes:
Author: uwe
Date: 2009-05-14 22:41:57 +0200 (Thu, 14 May 2009)
New Revision: 511
Modified:
trunk/flash.h
trunk/internal.c
trunk/nic3com.c
Log:
Factor out portable iopl()-style code into a global function
which all programmers can use, add missing close() call (trivial).
Signed-off-by: Uw
On Thu, May 14, 2009 at 11:48 AM, coreboot wrote:
> #136: failed to boot under KVM\QEMU
> -+--
> Reporter: silic...@... | Owner: somebody
> Type: defect | Status: new
>
On Thu, May 14, 2009 at 12:48 PM, Myles Watson wrote:
>
>
>> -Original Message-
>> From: Patrick Georgi [mailto:patr...@georgi-clan.de]
>> Sent: Thursday, May 14, 2009 11:13 AM
>> To: Myles Watson
>> Cc: coreboot
>> Subject: Re: [coreboot] [PATCH] Table code cleanup
>>
>> Am 14.05.2009 18:
On 23.03.2009 19:24, Tiago Marques wrote:
> Thanks! Got a change to try it out yesterday and it worked perfectly. No
> delays checking for SPI, worked as expected. Merge, please?
>
An alternative fix has been merged.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
--
coreboot mailing l
> -Original Message-
> From: coreboot-bounces+mylesgw=gmail@coreboot.org [mailto:coreboot-
> bounces+mylesgw=gmail@coreboot.org] On Behalf Of ron minnich
> Sent: Thursday, May 14, 2009 2:53 PM
> To: coreboot@coreboot.org
> Subject: Re: [coreboot] #136: failed to boot under KVM\QEM
Author: rminnich
Date: 2009-05-14 23:26:28 +0200 (Thu, 14 May 2009)
New Revision: 4285
Modified:
trunk/coreboot-v2/src/boot/selfboot.c
Log:
#136: failed to boot under KVM\QEMU
> -+--
> Reporter: silic...@?\226?\128?\166
Committed revision 4285.
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Fix compilation of nic3com on 64bit.
Signed-off-by: Carl-Daniel Hailfinger
Index: flashrom-nic3com_compilefix/flash.h
===
--- flashrom-nic3com_compilefix/flash.h (Revision 511)
+++ flashrom-nic3com_compilefix/flash.h (Arbeitskopie)
On Thu, May 14, 2009 at 12:33 PM, Robert Millan wrote:
> On Thu, May 14, 2009 at 10:17:48AM -0600, Myles Watson wrote:
>> Robert,
>>
>> Is there anything specific that I need to know with respect to where
>> the Multiboot table ends up? If you could give me memory ranges that
>> are acceptable, t
Hi All:
>From AMD Family 10h Processor BKDG (Rev D): a platform is capable of
having up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores.
Thus I am proposing to update the Options.lb as below:
Index: src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
==
I think one aspect of this is right, one is wrong
-void get_io_perms(void)
+void get_io_perms()
The void should be left in here I think.
{
#if defined (__sun) && (defined(__i386) || defined(__amd64))
if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
@@ -102,7 +102,7 @@
{
int ret
Acked-by:Ronald G. Minnich
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On Thu, May 14, 2009 at 11:28:32PM +0200, Carl-Daniel Hailfinger wrote:
> Fix compilation of nic3com on 64bit.
Thanks, I screwed up my last commit.
> Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Uwe Hermann
with the change below.
> Index: flashrom-nic3com_compilefix/internal.c
> ==
Author: hailfinger
Date: 2009-05-14 23:41:10 +0200 (Thu, 14 May 2009)
New Revision: 512
Modified:
trunk/flash.h
trunk/internal.c
trunk/nic3com.c
Log:
Fix compilation of nic3com on 64bit.
Signed-off-by: Carl-Daniel Hailfinger
Acked-by: Uwe Hermann
Modified: trunk/flash.h
=
On 14.05.2009 23:36, Uwe Hermann wrote:
> On Thu, May 14, 2009 at 11:28:32PM +0200, Carl-Daniel Hailfinger wrote:
>
>> Fix compilation of nic3com on 64bit.
>>
>
> Thanks, I screwed up my last commit.
>
Mistakes happen.
>> Signed-off-by: Carl-Daniel Hailfinger
>>
>
> Acked-by: Uw
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "rminnich" checked in revision 4285 to
the coreboot repository. This caused the following
changes:
Change Log:
#136: failed to boot under KVM\QEMU
> -+---
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Make the nic3com code check how many supported NICs are found. If we find
multiple ones, abort with a message to the user, suggesting to use the
Author: vlim
Date: 2009-05-15 00:00:28 +0200 (Fri, 15 May 2009)
New Revision: 4286
Modified:
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
Log:
>From AMD family 10h Processor BKDG (rev. D): a platform is capable of having
>up to 8 nodes, and each nodes supports 1,2,3,4
Author: vlim
Date: 2009-05-15 00:11:08 +0200 (Fri, 15 May 2009)
New Revision: 4287
Modified:
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
Log:
Trivia: remove comment
Signed-off-by: Vincent Lim
Acked-by: Vincent Lim
Modified: trunk/coreboot-v2/src/mainboard/amd/ser
On 14.05.2009 23:49, Uwe Hermann wrote:
> Make the nic3com code check how many supported NICs are found. If we find
> multiple ones, abort with a message to the user, suggesting to use the
>
> flashrom -p nic3com=bb:dd.f
>
> syntax. If exactly one supported NIC is found, use it. If none is found,
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "vlim" checked in revision 4286 to
the coreboot repository. This caused the following
changes:
Change Log:
>From AMD family 10h Processor BKDG (rev. D): a platform is capable of having
>up to 8 nodes, and each
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "vlim" checked in revision 4287 to
the coreboot repository. This caused the following
changes:
Change Log:
Trivia: remove comment
Signed-off-by: Vincent Lim
Acked-by: Vincent Lim
Build Log:
Compilation of
Author: uwe
Date: 2009-05-15 00:58:21 +0200 (Fri, 15 May 2009)
New Revision: 513
Modified:
trunk/flashrom.8
trunk/nic3com.c
Log:
Make the nic3com code check how many supported NICs are found. If we find
multiple ones, abort with a message to the user, suggesting to use the
flashrom -p nic
On Fri, May 15, 2009 at 12:16:09AM +0200, Carl-Daniel Hailfinger wrote:
> Please remove graphics cards and CD-ROM/DVD drives unless you have
> matching docs. I know that ATI graphics cards don't have sufficient
> documentation for flashing and I just checked with the contact I had who
> extended fl
On Thu, May 14, 2009 at 03:38:33PM +0200, Peter Stuge wrote:
> Hi Nathan,
>
> there was some discussion on the coreboot mailing list, and it seems
> that the SGABIOS binary doesn't have a checksum calculated for it,
> which means that some BIOSes refuse to initialize it.
>
> The SeaBIOS project m
[moving to coreb...@]
On 15.05.2009 00:58, Ward Vandewege wrote:
> On Thu, May 14, 2009 at 11:13:45PM +0200, Carl-Daniel Hailfinger wrote:
>
>> Can you please run
>> flashrom -V
>> and mail the output to us? This will help us to add support for your chip.
>>
>> On 14.05.2009 23:00, wangji wrote
2009/5/13 Uwe Hermann
> On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
> > Acked-by: Carl-Daniel Hailfinger
>
> Thanks, r499.
>
>
> Uwe.
> --
> http://www.hermann-uwe.de | http://www.holsham-traders.de
> http://www.crazy-hacks.org | http://www.unmaintained-free-software
Author: mjones
Date: 2009-05-15 01:42:41 +0200 (Fri, 15 May 2009)
New Revision: 4288
Modified:
trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h
trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
trunk/
On Mon, May 4, 2009 at 10:12 PM, Lim, Vincent wrote:
> I will test this configuration via SimNow, further improve if issues
> arise.
>
> Acked-by: Vincent Lim (vincent@amd.com)
Sorry for the delay. Just wanted to make sure that this doesn't break anyone.
Thanks Vincent!
r4288
Marc
--
http
(Please try not to full-quote.)
Carl-Daniel Hailfinger wrote:
> if erase fails halfway through, try to restore.
At the very least let the user decide if they really want all those
side effects. I think this will cause more problems than it solves.
//Peter
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On 15.05.2009 01:43, Peter Stuge wrote:
> (Please try not to full-quote.)
>
This was intentional because not everyone on the coreboot list is on the
flashrom alias.
> Carl-Daniel Hailfinger wrote:
>
>> if erase fails halfway through, try to restore.
>>
>
> At the very least let the use
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "mjones" checked in revision 4288 to
the coreboot repository. This caused the following
changes:
Change Log:
Update equivalent processor revision ID to load latest microcode patches and
register setting for all
On Fri, May 15, 2009 at 01:52:45AM +0200, Carl-Daniel Hailfinger wrote:
> On 15.05.2009 01:43, Peter Stuge wrote:
> > (Please try not to full-quote.)
> >
>
> This was intentional because not everyone on the coreboot list is on the
> flashrom alias.
Which should be a public mailing list, or _th
On Fri, May 15, 2009 at 02:31:52AM +0200, Uwe Hermann wrote:
> On Fri, May 15, 2009 at 01:52:45AM +0200, Carl-Daniel Hailfinger wrote:
> > On 15.05.2009 01:43, Peter Stuge wrote:
> > > (Please try not to full-quote.)
> > >
> >
> > This was intentional because not everyone on the coreboot list i
On Thu, 2009-05-14 at 22:51 +0800, FENG Yu Ning wrote:
> Carl-Daniel Hailfinger wrote:
> > Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
> > should handle such special opcode failure gracefully on ICH and
> > compatible chipsets.
>
> Acked-by: FENG Yu Ning
>
> iirc, Ru
On 15.05.2009 02:35, Ward Vandewege wrote:
> On Fri, May 15, 2009 at 02:31:52AM +0200, Uwe Hermann wrote:
>
>> On Fri, May 15, 2009 at 01:52:45AM +0200, Carl-Daniel Hailfinger wrote:
>>
>>> On 15.05.2009 01:43, Peter Stuge wrote:
>>>
(Please try not to full-quote.)
Author: hailfinger
Date: 2009-05-15 02:56:22 +0200 (Fri, 15 May 2009)
New Revision: 514
Modified:
trunk/spi.c
Log:
Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
should handle such special opcode failure gracefully on ICH and
compatible chipsets.
This fixes status reg
On 15.05.2009 02:45, Cristi Magherusan wrote:
> On Thu, 2009-05-14 at 22:51 +0800, FENG Yu Ning wrote:
>
>> Carl-Daniel Hailfinger wrote:
>>
>>> Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
>>> should handle such special opcode failure gracefully on ICH and
>>> c
Carl-Daniel Hailfinger wrote:
> > (Please try not to full-quote.)
>
> This was intentional because not everyone on the coreboot list is
> on the flashrom alias.
You seem to full-quote very often though. It helps (not just me;
everyone!) if you trim the quotes. Also in patch reviews. Thanks.
> >
Uwe Hermann wrote:
> > the flashrom alias.
>
> This closed, non-public alias is totally counter-productive
I don't consider it to be closed, and I don't think it should be.
Anyone who wants to get on it to help users should be able to do so.
But I think there's a point in having only people on t
It still failed on dbm690t + filo.
Do I have to patch the high_low.diff?
Zheng
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Myles Watson
Sent: Friday, May 15, 2009 4:55 AM
To: Patrick Georgi
Cc: coreboot
Subject: Re: [corebo
> It still failed on dbm690t + filo.
>
> Do I have to patch the high_low.diff?
No. Just that patch.
Could you send the output? With and without HAVE_HIGH_TABLES would be nice.
Thanks,
Myles
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#131: New flashrom motherboard support
-+--
Reporter: anonymous | Owner: somebody
Type: enhancement| Status: new
Priority: trivial| Miles
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