Hi All,
I've decided to use the coreboot to boot my development board SBC (single
board computer) which is required to boot Linux(ubuntu 8.10) as its payload.
My hardware configuration is:
1) INTEL ATOM CPU Z510P
2) INTEL SCH US15WP chipset
But i am confused about:
1) which coreboot version
yes, the hda is usually not partitioned.
What I do to boot, e.g., hda-linux.img or whatever
root (hd0)
kernel /vmlinuz root=/dev/hda
and then it is fine.
ron
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Mon, Jun 22, 2009 at 11:13 PM,
Anurag_Vashisthanurag_vashi...@satyam.com wrote:
Hi All,
I've decided to use the coreboot to boot my development board SBC (single
board computer) which is required to boot Linux(ubuntu 8.10) as its payload.
My hardware configuration is:
1) INTEL ATOM CPU
I got this message :
=
boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0
hda: LBA48 524MB: QEMU HARDDISK
Mounted ext2fs
Found Linux version 2.6.16.5 (r...@e-smith) #2 PREEMPT Sat Sep 22 00:14:46
Local time zone must be set--see bzImage.
Loading kernel... ok
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I'm wondering whether coreboot will work in my machine. Here is
requested information according to
http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F
1) System:
SAPPHIRE PI-AM2RS780G, AMDx86-64 QuadCore,
The cpuinfo is attached in
Hello all,
To start teh day, a small patch for an invalid local variable...
In C, local variable must be declared before any statment, and not, like in C++
in the middle of the function.
Make good use of it.
Regards,
Stephan.
Signed-off-by: Stephan Guilloux stephan.guill...@free.fr
Hi Alois,
On 23.06.2009 10:15, Alois Schlögl wrote:
I'm wondering whether coreboot will work in my machine. Here is
requested information [...]
1) System:
SAPPHIRE PI-AM2RS780G, AMDx86-64 QuadCore,
I have good and bad news for you.
The good news is that your processor is supported pretty
Hello all,
I'm facing some issues, with some flash ST M25P16.
When using flashrom (623), after programming, some bits are not programmed
correctly. Each time, the same bits are wrong, making the BIOS unusable.
In the file attached, the diff between what should be seen and and is really
Sorry, wrong part ID in the title.
The flash part is M25P16, not M26P16.
Selon stephan.guill...@free.fr:
Hello all,
I'm facing some issues, with some flash ST M25P16.
When using flashrom (623), after programming, some bits are not programmed
correctly. Each time, the same bits are wrong,
Konstantin,
I note that you have experience of the CN400. I am currently trying to
develop C3/CN400 support (Actually Luke CoreFusion) support, but I am
having diffculty with the early RAM init.
I've been looking at the VX800 code for comparison.
Other than the fact that the VX800 code is
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Carl-Daniel Hailfinger wrote:
Hi Alois,
On 23.06.2009 10:15, Alois Schlögl wrote:
I'm wondering whether coreboot will work in my machine. Here is
requested information [...]
1) System:
SAPPHIRE PI-AM2RS780G, AMDx86-64 QuadCore,
I have good
Hi Ron,
ron minnich wrote:
I arrive berlin 10:42 or so. I do want to see the brandenberg gate
at some point in the day.
After the expo on Thursday there is the LinuxNacht social event. Want
to get there not too late to get some food from the buffet. :)
I guess maybe do sightseeing first, or
stephan.guill...@free.fr wrote:
Hello all,
To start teh day, a small patch for an invalid local variable...
In C, local variable must be declared before any statment, and not, like in
C++
in the middle of the function.
Thanks a lot for the patch!
The restriction of local variable
Selon Stefan Reinauer ste...@coresystems.de:
stephan.guill...@free.fr wrote:
Hello all,
To start teh day, a small patch for an invalid local variable...
In C, local variable must be declared before any statment, and not, like in
C++
in the middle of the function.
Thanks a lot
Anurag_Vashisth wrote:
My hardware configuration is:
1) INTEL ATOM CPU Z510P
2) INTEL SCH US15WP chipset
Dear Anurag,
There is currently no support for this CPU/chipset combination available.
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761
stephan.guill...@free.fr wrote:
Selon Stefan Reinauer ste...@coresystems.de:
stephan.guill...@free.fr wrote:
Hello all,
To start teh day, a small patch for an invalid local variable...
In C, local variable must be declared before any statment, and not, like in
C++
Author: stepan
Date: 2009-06-23 12:44:36 +0200 (Tue, 23 Jun 2009)
New Revision: 624
Modified:
trunk/physmap.c
Log:
There are some non-C99 compilers out there used to compile flashrom.
This fixes compilation for them.
Signed-off-by: Stephan Guilloux stephan.guill...@free.fr
Acked-by: Stefan
The akefile rules for %.o and flashrom.o are identical. Let %.o handle
flashrom.o as well.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-makefile_cleanup/Makefile
===
---
Author: hailfinger
Date: 2009-06-23 13:33:43 +0200 (Tue, 23 Jun 2009)
New Revision: 625
Added:
trunk/serprog.c
Modified:
trunk/Makefile
trunk/flash.h
trunk/flashrom.c
Log:
Initial commit of an external serial flasher protocol.
Supports RS-232, USB serial converters (untested) and TCP
On Tue, Jun 23, 2009 at 12:32:05PM +0200, Stefan Reinauer wrote:
stephan.guill...@free.fr wrote:
Hello all,
To start teh day, a small patch for an invalid local variable...
In C, local variable must be declared before any statment, and not, like in
C++
in the middle of the
On Tue, Jun 23, 2009 at 12:49:55PM +0200, Carl-Daniel Hailfinger wrote:
The akefile rules for %.o and flashrom.o are identical. Let %.o handle
flashrom.o as well.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Index: flashrom-makefile_cleanup/Makefile
On 17.06.2009 00:32, Urja Rannikko wrote:
Support for an external serial flasher protocol.
Supports RS-232, USB serial converters (untested) and TCP streams.
Signed-off-by: Urja Rannikko urja...@gmail.com
---
Here we go with the third iteration of this patch - now rebased to r598.
Also
On 23.06.2009 10:42, stephan.guill...@free.fr wrote:
To start teh day, a small patch for an invalid local variable...
In C, local variable must be declared before any statment, and not, like in
C++
in the middle of the function.
Signed-off-by: Stephan Guilloux stephan.guill...@free.fr
Author: hailfinger
Date: 2009-06-23 13:48:37 +0200 (Tue, 23 Jun 2009)
New Revision: 626
Modified:
trunk/Makefile
Log:
The makefile rules for %.o and flashrom.o are identical. Let %.o handle
flashrom.o as well.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Acked-by:
On 23.06.2009 13:40, Luc Verhaegen wrote:
On Tue, Jun 23, 2009 at 12:49:55PM +0200, Carl-Daniel Hailfinger wrote:
The makefile rules for %.o and flashrom.o are identical. Let %.o handle
flashrom.o as well.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Hi, Luc,
I agree we should set standards as low as possible, and try to make it
easier for people to write good code, but..
On 23.06.2009 13:39 Uhr, Luc Verhaegen wrote:
I personally dislike this, as it is only done to make it easier for
people to be lazy.
Or to make the code more
On 14.06.2009 20:23, Urja Rannikko wrote:
Support for an external serial flasher protocol.
Supports RS-232, USB serial converters (untested) and TCP streams.
Signed-off-by: Urja Rannikko urja...@gmail.com
Serial Flasher Protocol Specification - version 1 (0x01 return value == 1)
Command
On 23.06.2009 13:44, Carl-Daniel Hailfinger wrote:
On 17.06.2009 00:32, Urja Rannikko wrote:
Support for an external serial flasher protocol.
Supports RS-232, USB serial converters (untested) and TCP streams.
Signed-off-by: Urja Rannikko urja...@gmail.com
The remainder of your
Add stubs for the TotalPhase Cheetah SPI programmer.
The programmer code is not finished yet, but the glue code is extremely
painful to carry forward especially because these areas in flash.h,
flashrom.c, flashrom.8 and Makefile are touched each time someone adds
another external programmer to
On Tue, Jun 23, 2009 at 01:51:21PM +0200, Stefan Reinauer wrote:
Hi, Luc,
I agree we should set standards as low as possible, and try to make it
easier for people to write good code, but..
On 23.06.2009 13:39 Uhr, Luc Verhaegen wrote:
I personally dislike this, as it is only done to make
On Tue, Jun 23, 2009 at 01:51:06PM +0200, Carl-Daniel Hailfinger wrote:
On 23.06.2009 13:40, Luc Verhaegen wrote:
On Tue, Jun 23, 2009 at 12:49:55PM +0200, Carl-Daniel Hailfinger wrote:
The makefile rules for %.o and flashrom.o are identical. Let %.o handle
flashrom.o as well.
On Mon, Jun 01, 2009 at 09:33:05PM +0200, Peter Stuge wrote:
Patrick Georgi wrote:
Hi,
attached patch fixes an oversight in cbfstool related to bootblock
handling.
With this patch, cbfstool reacts to a too large bootblock file by stopping
with an error code. Before, it did whatever
On Tue, 23 Jun 2009 15:49:17 +0200
Uwe Hermann u...@hermann-uwe.de wrote:
On Sat, Jun 06, 2009 at 01:16:43AM +0400, Alexander Gordeev wrote:
I've tested Gigabyte GA-EP35-DS3L board
(http://www.gigabyte.com.tw/Products/Motherboard/Products_Overview.aspx?ProductID=2778)
and it is supported
Selon Luc Verhaegen l...@skynet.be:
On Tue, Jun 23, 2009 at 01:51:21PM +0200, Stefan Reinauer wrote:
Hi, Luc,
I agree we should set standards as low as possible, and try to make it
easier for people to write good code, but..
On 23.06.2009 13:39 Uhr, Luc Verhaegen wrote:
I
Really ?
No one can help ?
Selon stephan.guill...@free.fr:
Hello all,
I'm facing some issues, with some flash ST M25P16.
When using flashrom (623), after programming, some bits are not programmed
correctly. Each time, the same bits are wrong, making the BIOS unusable.
In the file
Note that I'm facing this on 3 boards. The 4th one is working properly.
On each non working board, some bits are wrong, but they are not the
same, on
each board.
My best guess would be a timing issue. Is there a way that you can lengthen
the default delays to something safer but not too
IIRC this variable declaration in the middle of a code block has been
an issue in the linux kernel as well, and variable declarations in the
midst of code is not allowed.
It comes from C++. ANSI C++ allows it. I thought that ANSI C did too. Ah well.
ron
--
coreboot mailing list:
Selon Myles Watson myle...@gmail.com:
Note that I'm facing this on 3 boards. The 4th one is working properly.
On each non working board, some bits are wrong, but they are not the
same, on
each board.
My best guess would be a timing issue. Is there a way that you can lengthen
the
Note that I'm facing this on 3 boards. The 4th one is working
properly.
On each non working board, some bits are wrong, but they are not the
same, on
each board.
My best guess would be a timing issue. Is there a way that you can
lengthen
the default delays to something safer
Selon Myles Watson myle...@gmail.com:
Note that I'm facing this on 3 boards. The 4th one is working
properly.
On each non working board, some bits are wrong, but they are not the
same, on
each board.
My best guess would be a timing issue. Is there a way that you can
Given that I would look at the actual flash routines that get used and
see
if there are timing parameters that you can play with.
I checked the code, there is no timing...
From what I saw, flashrom just waits for the status returned by the flash
itself.
OK. Then it's possible that
Selon Myles Watson myle...@gmail.com:
Given that I would look at the actual flash routines that get used and
see
if there are timing parameters that you can play with.
I checked the code, there is no timing...
From what I saw, flashrom just waits for the status returned by the flash
Uwe Hermann wrote:
Hi,
On Sat, Jun 20, 2009 at 02:34:24AM +0100, Andrew Morgan wrote:
Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir',
and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III
motherboard.
Thanks, please see attached patch for a first attempt at
Some news for this issue.
It looks to be hardware, on some parts :
We tried to increase or decrease the board temperature, and then, some
non working flash work with a lower temperature...
So, flashrom looks to be safe ;-)
stephan.guill...@free.fr a écrit :
Really ?
No one can help ?
Selon
On Tue, Jun 23, 2009 at 12:42 PM, Thomas JOURDAN
thomas.jour...@gmail.comwrote:
Hi
This series of patches add support in coreboot-v2 for the Intel Eagle
Heights evaluation board
Welcome to the project!
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
If you sign off your
Signed-off-by: Thomas Jourdan thomas.jour...@gmail.com
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Properly check whether get_io_perms() worked and propagate errors (if any).
Also, call programmer_shutdown() whenever we exit(). Actually,
Hi
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
If you sign off your patches they can be reviewed, acked, and committed.
Done !
You could try having SeaBIOS enable your ROM. There have been several cases
where SeaBIOS was less picky than the others.
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
If you sign off your patches they can be reviewed, acked, and committed.
Done !
Thanks. As I glanced through I didn't see any copyright lines from you. It
would speed the reviewing process if you sent the patch as a
I'm replying from my phone with opera mini, so sorry bad formatting/short text.
On 2009-06-23, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote:
On 14.06.2009 20:23, Urja Rannikko wrote:
Support for an external serial flasher protocol.
Supports RS-232, USB serial converters
On Mon, Jun 22, 2009 at 11:57:03AM +0200, Carl-Daniel Hailfinger wrote:
Check result of all SPI erase functions.
Since block erase functions do not know the block length (it's not
specified in any standard), block erase functions now get an additional
parameter blocklen. This enables flashrom
On Mon, Jun 22, 2009 at 11:26:54AM +0200, Carl-Daniel Hailfinger wrote:
Updated patch.
Use correct abstraction for verify_range(). The new abstraction can
handle out-of-band chip communication protocols as well.
The old abstraction caused spurious false positives for erase on SPI and
Uwe Hermann wrote:
Hi,
On Sat, Jun 20, 2009 at 02:34:24AM +0100, Andrew Morgan wrote:
Here is the output of 'lspci -tvnn', 'superiotool -dV', 'getpir',
and 'mptable' run on the (beautifully named) Soyo SY-6BA+ III
motherboard.
Thanks, please see attached patch for a first attempt at
Author: uwe
Date: 2009-06-24 02:35:07 +0200 (Wed, 24 Jun 2009)
New Revision: 4369
Added:
trunk/coreboot-v2/src/mainboard/soyo/
trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/
trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Config.lb
On Wed, Jun 24, 2009 at 12:25:51AM +0100, Andrew Morgan wrote:
Acked-by: Andrew Morgan zil...@ziltro.com
It boots FILO Linux!
ROM size is correct.
NIC is not on-board, it is a PCI card.
FILO was too large for a 256 KB ROM to be included with both
normal and fallback images, only tested
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer uwe checked in revision 4369 to
the coreboot repository. This caused the following
changes:
Change Log:
Add support for the Soyo SY-6BA+ III board.
Tested on hardware by Andrew Morgan zil...@ziltro.com, boots
I got this message :
=
boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0
hda: LBA48 524MB: QEMU HARDDISK
Mounted ext2fs
Found Linux version 2.6.16.5 (r...@e-smith) #2 PREEMPT Sat Sep 22 00:14:46
Local time zone must be set--see bzImage.
Loading kernel... ok
On Tue, Jun 23, 2009 at 7:06 PM, Rick Ant rick_...@yahoo.com wrote:
I got this message :
=
boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0
hda: LBA48 524MB: QEMU HARDDISK
Mounted ext2fs
Found Linux version 2.6.16.5 (r...@e-smith) #2 PREEMPT Sat Sep
Hello,
then I will burn the bios.bin into the flash ROM chip 49LF004, the original
BIOS system will be removed ?
and
disk.img into Compact flash...
Am I right in this point ?
Thanks
--- On Tue, 6/23/09, David Hendricks david.hendri...@gmail.com wrote:
From: David Hendricks
I try to install Flash ROM,
but need zlib-devel and pciutils-devel,
I'm using Suse 10.1,
Can I install Coreboot + payload Linux without any Compact flash?
All in the Flash ROM chip ?
Anyone knows where to download those files ?
Thanks
--
coreboot mailing list:
Correct, the original BIOS image will be removed / replaced with your new
Coreboot image.
I recommend that you test your system image (disk.img?) separately from your
Coreboot image. There are many, many things that can go wrong in this
process. If you try to apply all of your changes at once, it
don't forget the wonderfulness of earlyprintk when booting a linux
kernel and you are not sure if it is right.
you just append it to the command line. Here is one example. I use
'keep' when I'm really being paranoid.
earlyprintk=ttyS0,115200,keep
ron
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