Hello folks!
You are doing a great job!
I buy a ASUS P6T (socket1366) with a broken VT-d. (VT-x Okay: vmx on) core i7
920.
http://www.nabble.com/Re:-Re:-VT-D-RMRR-is-incorrect-p22022061.html
I'd like to know if your project is still quite active, if you plan to support
this motherboard, and
On Mon, 26 Oct 2009 20:12:33 -0700, ron minnich rminn...@gmail.com wrote:
silly question:
why, in a 45-line high window, does it only let me see 6 mainboards at
a time in menuconfig?
not sure?
Would be oh-so-cool when demo'ing this to have the huge number of
vendors show up ...
Yes
Below are three small patches, they all seemed useful while I have been
working with VGA option ROMs.
Thanks for the great work.
MM
Use more care when implimenting the PCI BIOS functions.
The 'CHECK' function seemed to be both wrong code and the wrong
number, so I have just added the corrct
Hello
as Uwe sugested, i checked abuild -a, and found one romcc prototype
problem, fixed patch in attachment.
best regards
Maciej
--
Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161
POE/Perl user
coreboot-4869-prototypes-updated.patch
Description: Binary data
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coreboot mailing
What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to
execution of the very first instruction?
I recall that it's impossible to execute code directly in an SPI chip.
or am I missing something?
--
Regards,
Darmawan Salihun
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index: src/lib/clog2.c
===
--- src/lib/clog2.c (revision 4869)
+++ src/lib/clog2.c (working copy)
@@ -7,6 +7,8 @@
/* Assume 8 bits per byte */
On 27/10/2009, Myles Watson myle...@gmail.com wrote:
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index: src/lib/clog2.c
===
--- src/lib/clog2.c (revision 4869)
+++ src/lib/clog2.c (working
On Tue, Oct 27, 2009 at 7:32 AM, Maciej Pijanka maciej.pija...@gmail.comwrote:
On 27/10/2009, Myles Watson myle...@gmail.com wrote:
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index: src/lib/clog2.c
Author: myles
Date: 2009-10-27 15:05:21 +0100 (Tue, 27 Oct 2009)
New Revision: 4870
Modified:
trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
Log:
Update arima/hdama to detect how many nodes there are. Compare to tyan/s2892.
Fixes booting for Hugh.
Various white space fixes
On 27/10/2009, Myles Watson myle...@gmail.com wrote:
On Tue, Oct 27, 2009 at 7:32 AM, Maciej Pijanka
maciej.pija...@gmail.comwrote:
On 27/10/2009, Myles Watson myle...@gmail.com wrote:
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index:
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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Author: myles
Date: 2009-10-27 15:29:29 +0100 (Tue, 27 Oct 2009)
New Revision: 4871
Modified:
trunk/coreboot-v2/src/arch/i386/boot/gdt.c
trunk/coreboot-v2/src/arch/i386/boot/tables.c
trunk/coreboot-v2/src/arch/i386/include/div64.h
trunk/coreboot-v2/src/arch/i386/lib/exception.c
On Tue, Oct 27, 2009 at 8:20 AM, Myles Watson myle...@gmail.com wrote:
Acked-by: Myles Watson myle...@gmail.com
Rev 4871.
Thanks,
Myles
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In v3 IIRC we decided on an include file, lib.h, which had these sorts
of nuisance prototypes.
ron
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On Tue, Oct 27, 2009 at 8:58 AM, ron minnich rminn...@gmail.com wrote:
In v3 IIRC we decided on an include file, lib.h, which had these sorts
of nuisance prototypes.
Something like that would be fine with me, but since we'd do it just to do
it, not to make the code cleaner, maybe it's just as
Add $(obj) paths for a couple of smm files so they don't end up in the top
directory.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Index: svn/src/cpu/x86/smm/Makefile.inc
===
--- svn.orig/src/cpu/x86/smm/Makefile.inc
On Tue, Oct 27, 2009 at 8:20 AM, Myles Watson myle...@gmail.com wrote:
Add $(obj) paths for a couple of smm files so they don't end up in the top
directory.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Ronald G. Minnich rminn...@gmail.com
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coreboot mailing list:
Author: myles
Date: 2009-10-27 16:53:27 +0100 (Tue, 27 Oct 2009)
New Revision: 4872
Modified:
trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc
Log:
Add $(obj) paths for a couple of smm files so they don't end up in the top
directory.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by:
On Tue, Oct 27, 2009 at 9:51 AM, ron minnich rminn...@gmail.com wrote:
On Tue, Oct 27, 2009 at 8:20 AM, Myles Watson myle...@gmail.com wrote:
Add $(obj) paths for a couple of smm files so they don't end up in the
top
directory.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by:
On Tue, Oct 27, 2009 at 8:17 AM, Myles Watson myle...@gmail.com wrote:
Something like that would be fine with me, but since we'd do it just to do
it, not to make the code cleaner, maybe it's just as good to put the
prototypes by the functions.
In the case of that function you need a proto
On Tue, Oct 27, 2009 at 10:10 AM, ron minnich rminn...@gmail.com wrote:
On Tue, Oct 27, 2009 at 8:17 AM, Myles Watson myle...@gmail.com wrote:
Something like that would be fine with me, but since we'd do it just to
do
it, not to make the code cleaner, maybe it's just as good to put the
Author: myles
Date: 2009-10-27 17:24:22 +0100 (Tue, 27 Oct 2009)
New Revision: 4873
Modified:
trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c
trunk/coreboot-v2/src/lib/cbmem.c
Log:
Remove redundant declarations. Trivial.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson
These look really good to me anyway, maybe someone can give them a test?
ron
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Build-tested on ASUS P2B-F where 80% of the warnings are now gone.
Uwe.
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Improve coreboot build output and eliminate some warnings:
- Add static and const where
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public
dochttp://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf
:
3.3 BIOS RAM
The SB700 has 256 bytes of BIOS
On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks dhend...@google.com wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public doc:
3.3 BIOS RAM
The SB700 has
On Tue, Oct 27, 2009 at 1:40 PM, Uwe Hermann u...@hermann-uwe.de wrote:
Build-tested on ASUS P2B-F where 80% of the warnings are now gone.
Great.
Index: src/arch/i386/boot/gdt.c
===
--- src/arch/i386/boot/gdt.c(Revision 4873)
On Tue, Oct 27, 2009 at 2:04 PM, Gregg Levine gregg.drw...@gmail.comwrote:
On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks dhend...@google.com
wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
What is the BIOS RAM in AMD SB7XX used for?
Author: uwe
Date: 2009-10-27 22:49:33 +0100 (Tue, 27 Oct 2009)
New Revision: 4874
Modified:
trunk/coreboot-v2/Makefile
trunk/coreboot-v2/src/arch/i386/boot/gdt.c
trunk/coreboot-v2/src/arch/i386/boot/tables.c
trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c
On Tue, Oct 27, 2009 at 03:09:15PM -0600, Myles Watson wrote:
With the %p:
Acked-by: Myles Watosn myle...@gmail.com
Thanks, r4874.
Uwe.
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-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi,
I have some questions:
1) is 0x600 as base for lowmem trampoline safe? it always makes me wonder, this
was the reason why I did the realmode code which runs above 1MB ;) Maybe we can
have that too and only copy the trampoline to the highmem save
Author: uwe
Date: 2009-10-28 00:14:54 +0100 (Wed, 28 Oct 2009)
New Revision: 4875
Modified:
trunk/coreboot-v2/Makefile
trunk/coreboot-v2/src/arch/i386/Makefile.inc
trunk/coreboot-v2/util/cbfstool/Makefile.inc
trunk/coreboot-v2/util/sconfig/config.g
On 27.10.2009 21:51, David Hendricks wrote:
On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun wrote
What is the BIOS RAM in AMD SB7XX used for?
Looks like scratchpad memory to me. From the public
dochttp://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf
:
3.3 BIOS RAM
The
On 27.10.2009 14:06, Darmawan Salihun wrote:
What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to
execution of the very first instruction?
No.
I recall that it's impossible to execute code directly in an SPI chip.
Yes, but the
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