Here is a patch for inteltool to print the registers values
for the P31..Q35 chipset. The registers are (as far as I
can tell) unchanged with respect to those of the PM965.
I've no strong ideas on the names: I've chosen
PCI_DEVICE_ID_INTEL_82[PQG]3[135] as Northbridge
names, they can
Mansoor wrote:
maybe the graphics driver in Linux has the ability to initialize
hardware completely?
I tried this option. But it didn't initialize VGA
Ok. If you prefer this solution you could, as I mentioned, try to
contact the Linux graphics driver developers. There are people from
Intel
If anyone does want to work on the D945GCLF board then you need to
update the sdram_enable_memory_clocks in
northbridge/intel/i945/raminit.c in a way that does not break the mobile
version. The desktop version of the chipset has more clocks and so uses
more bits in C0DCLKDIS and C1DCLKDIS to
On Mon, Nov 02, 2009 at 02:25:23PM +0800, Bao, Zheng wrote:
Now I found that the system doesn't hang. It just decompresses the
image. It is unbearably slow. Do you guys know why it does so slowly?
Ah! I saw that too on Fam10. Mansoor suggested setting
CONFIG_XIP_ROM_BASE
to solve this. Does
Author: hailfinger
Date: 2009-11-02 16:01:49 +0100 (Mon, 02 Nov 2009)
New Revision: 4905
Modified:
trunk/util/inteltool/inteltool.c
trunk/util/inteltool/inteltool.h
trunk/util/inteltool/memory.c
trunk/util/inteltool/pcie.c
Log:
Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
The
On 02.11.2009 10:12, Loïc Grenié wrote:
Here is a patch for inteltool to print the registers values
for the P31..Q35 chipset. The registers are (as far as I
can tell) unchanged with respect to those of the PM965.
I've no strong ideas on the names: I've chosen
Myles,
Setting it to 1 or 2 gives what looks like the same output. It causes
coreboot to fail with the following error:
Initializing CBMEM area to 0x3fff (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 3fff0200...ok
High Tables Base is 3fff.
Copying Interrupt Routing Table to
Setting it to 1 or 2 gives what looks like the same output. It causes
coreboot to fail with the following error:
I guess I shouldn't have committed it until it worked, but 0 was the wrong
value.
Initializing CBMEM area to 0x3fff (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to
If the coreboot and filo overlap, it will slice off a piece at the
beginning or end. In the beginning case, a new segment is inserted
before the current one. The ptr will move forward and doesn't seem to
have any chance to process the new segment.
ptr -+ move ---
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