[coreboot] Hint for boot from a PCI device.

2010-01-24 Thread vvv
How about debuging/loading/using coreboot from a PCI device? Quote from Intel I/O Controller Hub 9 (ICH9) Family Datasheet: CS—General Control and Status Register Offset Address: 3410–3413h Attribute: R/W, R/WLO Default Value: 0yy0h (yy = xxx0b)Size:32-bit Boot

Re: [coreboot] Hint for boot from a PCI device.

2010-01-24 Thread Stefan Reinauer
On 1/24/10 10:27 AM, v...@ru.ru wrote: How about debuging/loading/using coreboot from a PCI device? Do you have a pointer to appropriate PCI cards? I guess Robson/TurboMemory cards won't work, will they? Stefan -- coreboot mailing list: coreboot@coreboot.org

[coreboot] [commit] r5049 - trunk/util/superiotool

2010-01-24 Thread svn
Author: uwe Date: 2010-01-24 18:15:25 +0100 (Sun, 24 Jan 2010) New Revision: 5049 Modified: trunk/util/superiotool/README Log: Update list of superiotool contributors to r5048 (trivial). The list is mostly generated by grepping for Signed-off-by in 'svn log'. Signed-off-by: Uwe Hermann

[coreboot] [commit] r5050 - trunk/util/superiotool

2010-01-24 Thread svn
Author: uwe Date: 2010-01-24 18:29:38 +0100 (Sun, 24 Jan 2010) New Revision: 5050 Modified: trunk/util/superiotool/README Log: Document CONFIG_PCI usage in the README (trivial). Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Modified:

Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

2010-01-24 Thread Stefan Reinauer
On 1/23/10 5:43 PM, Samuel D. wrote: I don't have any way to test this patch right now, so I'll just add it in upcoming 4.01. Thanks for your work. Sam. Dear Sam, there was an additional bug I introduced. On top of the other patch, you need to apply this: * Index: coreboot.c

[coreboot] [PATCH]some more kconfig

2010-01-24 Thread Patrick Georgi
Hi, the following patch aligns several kconfig options to match newconfig: HT_CHAIN_UNITID_BASE HT_CHAIN_END_UNITID_BASE SB_HT_CHAIN_ON_BUS0 SB_HT_CHAIN_UNITID_OFFSET_ONLY MAX_CPUS MAX_PHYSICAL_CPUS ROM_SIZE TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 Signed-off-by: Patrick Georgi

Re: [coreboot] [PATCH]some more kconfig

2010-01-24 Thread Stefan Reinauer
On 1/25/10 12:03 AM, Patrick Georgi wrote: Hi, the following patch aligns several kconfig options to match newconfig: HT_CHAIN_UNITID_BASE HT_CHAIN_END_UNITID_BASE SB_HT_CHAIN_ON_BUS0 SB_HT_CHAIN_UNITID_OFFSET_ONLY MAX_CPUS MAX_PHYSICAL_CPUS ROM_SIZE TSC_X86RDTSC_CALIBRATE_WITH_TIMER2

[coreboot] [commit] r5051 - in trunk/src/mainboard: a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 advantech/pcm-5820 amd/db800 amd/dbm690t amd/norwich amd/pistachio amd/rumba arima/hdama artecgro

2010-01-24 Thread svn
Author: oxygene Date: 2010-01-25 08:56:01 +0100 (Mon, 25 Jan 2010) New Revision: 5051 Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig trunk/src/mainboard/a-trend/atc-6240/Kconfig trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/src/mainboard/advantech/pcm-5820/Kconfig