Am 25.01.2010 17:13, schrieb Knut Kujat:
> - booting interrupts for about 4 minutes on "Stage: loading
> fallback/coreboot_ram @ 0x20 (360448 bytes), entry @ 0x20"
>
For this issue, the following change might help:
--- src/cpu/amd/mtrr/amd_earlymtrr.c(revision 5054)
+++ src/cpu/amd/m
Patrick Georgi escribió:
> Am 25.01.2010 17:13, schrieb Knut Kujat:
>
>> - booting interrupts for about 4 minutes on "Stage: loading
>> fallback/coreboot_ram @ 0x20 (360448 bytes), entry @ 0x20"
>>
>>
> For this issue, the following change might help:
> --- src/cpu/amd/mtrr/amd_e
Added the code/cache setup comments and stripped whitespace changes, hope this
is to the liking of everyone :)
Edwin
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Patrick Georgi
Sent: 25 January 2010 17:13
To: coreboot@co
Am 26.01.2010 11:58, schrieb Edwin Beasant:
>
> Added the code/cache setup comments and stripped whitespace changes,
> hope this is to the liking of everyone J
>
Looks good to me, thank you!
We still need your signature before we can commit it, see
http://www.coreboot.org/Development_Guidelines#Sig
Author: oxygene
Date: 2010-01-26 12:22:43 +0100 (Tue, 26 Jan 2010)
New Revision: 5055
Modified:
trunk/src/cpu/amd/model_lx/cache_as_ram.inc
trunk/src/mainboard/amd/db800/cache_as_ram_auto.c
Log:
- Clean up and comment writing of MSRs for cache control (Backport from v3)
- Invalidate Cache Ta
Am 26.01.2010 12:15, schrieb Edwin Beasant:
> Patch to fix AMD Geode LX booting of Coreboot:
>
> This patch introduces the following:
>
> - Cleaned up and commented writing of MSR’s for cache control
> (Backport from v3)
>
> - Invalidates Cache Tags (by means of in-place rewrite
This patch adds e- and f-segment as an available RAM area on the AMD
lx-northbridge platforms.
- Allows SeaBios to become resident correctly
Signed-off-by: Edwin Beasant
coreboot-trunk-geode-efsegment-map.patch
Description: coreboot-trunk-geode-efsegment-map.patch
--
coreboot mailin
Author: stepan
Date: 2010-01-26 15:09:30 +0100 (Tue, 26 Jan 2010)
New Revision: 5056
Modified:
trunk/util/mptable/Makefile
trunk/util/mptable/mptable.c
Log:
use stdint types for structures, and don't use pointers
for fields defined 32bit in the multi processor specification.
Also, fix lots
Am 26.01.2010 13:00, schrieb Edwin Beasant:
> This patch adds e- and f-segment as an available RAM area on the AMD
> lx-northbridge platforms.
>
> - Allows SeaBios to become resident correctly
> Signed-off-by: Edwin Beasant
I commit it with a-b excluded - not sure if they have to
I tried it with and without the little patch below ( and of course with
the "big" patch) and it freezes after 2 seconds:
Memtest86+ v4.00 | Pass 0%
AMD K10 (65nm) @ 2000 MHz | Test 3% #
L1 Cache: 64K 30303 MB/s | Test #0 [Address test, walking ones]
L2 Cache: 512K 10050 MB/s
Knut,
are the values the same as with the vendor bios? Do you get any errors
at all, or does it just hang?
Stefan
On 1/26/10 5:48 PM, Knut Kujat wrote:
> I tried it with and without the little patch below ( and of course with
> the "big" patch) and it freezes after 2 seconds:
>
> Memtest86+ v4.0
I haven't tried with a unpatched version of memtest86+ 4.0 and it works
with vendor BIOS. Now with the patched version it halts with coreboot
without error messages (the output you see below is what I see until I
press reset button) and with vendor BIOS its reboots at the same point
(after 2 sec).
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