On Mon, Feb 15, 2010 at 9:37 PM, ron minnich wrote:
> On Mon, Feb 15, 2010 at 6:47 PM, Myles Watson wrote:
>
>> I'm not sure it was right in newconfig. Doesn't it have to be larger than
>> that (8K)? I thought it had to be 32K for lzma. The other reason for the
>> stack being larger is page ta
On Mon, Feb 15, 2010 at 6:47 PM, Myles Watson wrote:
> I'm not sure it was right in newconfig. Doesn't it have to be larger than
> that (8K)? I thought it had to be 32K for lzma. The other reason for the
> stack being larger is page tables for memory initialization, right?
I thought marc was
Here is a cleaned up and tested version of the SMP APIC autodetect patch.
Signed-off-by: Timothy Pearson
---
It would of course be helpful to attach the patch. My Webmail client
keeps eating it...
Timothy Pearson
Raptor Engineering
--- /tahoe/coreboot_original/coreboot/src/arch/i386/smp/mpsp
Here is a cleaned up and tested version of the SMP APIC autodetect patch.
Signed-off-by: Timothy Pearson
---
Let me know what you think!
Timothy Pearson
Raptor Engineering
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> -Original Message-
> From: coreboot-bounces+mylesgw=gmail@coreboot.org [mailto:coreboot-
> bounces+mylesgw=gmail@coreboot.org] On Behalf Of Marc Jones
> Sent: Monday, February 15, 2010 5:05 PM
> To: Coreboot
> Subject: [coreboot] [patch] fix fam10 stack size
>
> Adjust the FAM1
Acked-by: Ronald G. Minnich
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2010/2/13 Zheng Bao :
>
>
>> Date: Sat, 13 Feb 2010 11:23:49 -0700
>> Subject: Re: [coreboot] Data in memory changes unexpectedly
>> ininitialize_cpus
>> From: marcj...@gmail.com
>> To: fishb...@hotmail.com
>> CC: coreboot@coreboot.org
>>
>> 2010/2/12 Zheng Bao :
>> >
>> >
>> >> Date: Fri, 12 Feb 2
Author: stepan
Date: Tue Feb 16 01:06:42 2010
New Revision: 5130
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5130
Log:
fix APCI typos.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/arch/i386/include/arch/acpi.h
trunk/src/northbridge/amd/amdht/A
Adjust the FAM10 stack size to match newconfig.
Signed-off-by: Marc Jones
--
http://se-eng.com
fam10_stacksize.patch
Description: Binary data
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Author: stepan
Date: Tue Feb 16 00:27:48 2010
New Revision: 5129
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5129
Log:
fix clock polling in pc97317 driver.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/superio/nsc/pc97317/pc97317_early_serial.c
M
Author: uwe
Date: Tue Feb 16 00:24:51 2010
New Revision: 5128
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5128
Log:
Document the reason for r5124 in the code/Makefile (trivial).
Signed-off-by: Uwe Hermann
Acked-by: Uwe Hermann
Modified:
trunk/Makefile
Modified: trunk/Makefile
I always refresh in the hope that the latest revision will magically
work :) However see
http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/superio/nsc/pc97317/pc97317_early_serial.c#L4
peter
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Ticket
Owner
Status
Description
#157 ste...@coresystems.de new utils/inteltool has outdated pciutils check in Makefile
#156 ste...@coresystems.de new Add Layout File capability to v3 and LAR tool
#155 ke...@koconnor.net
On 2/14/10 11:02 PM, Peter Bannis wrote:
> You are not confused. It should be
> while(!(inb(PM_BASE + 1) & 0x80))
>
> but the current code has
> while(!inb(PM_BASE + 1 & 0x80))
>
> either way incorrect code to read port 0x80 is generated instead of
> reads to port (0xe8+1):
Not here. You should pro
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