Am 15.04.2010 01:58, schrieb repository service:
> $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S
> @printf "CC $(subst $(obj)/,,$(@))\n"
> - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include
> -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.
Author: myles
Date: Thu Apr 15 07:19:29 2010
New Revision: 5440
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5440
Log:
Remove a few more warnings from fam10.
Signed-off-by: Myles Watson
Acked-by: Myles Watson
Modified:
trunk/src/cpu/amd/microcode/microcode.c
trunk/src/cpu/am
2010/4/14 Keith Hui
> Hi all,
>
> Based on Idwer's RFC I tried adding ACPI to P2B-LS plus completing the
> rest of the PIIX4 function 3 initialization.
>
> This is a summary of what I did:
>
> * I used the DSDT table from the final vendor BIOS. Not provided here
> for obvious reasons, but I can t
that would be very good, if you can mail me the board. But i would like to
try order one first.
On Wed, Apr 14, 2010 at 9:06 AM, Scott Olsen wrote:
> Thank you very much. I have an extra board that I could mail to you if
> that would help?
>
>
> Scott
>
>
>
> On Tue, Apr 13, 2010 at 10:39 AM, Q
Author: stepan
Date: Thu Apr 15 01:58:07 2010
New Revision: 5439
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5439
Log:
get rid of this nerving crt0.d stuff
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/arch/i386/Makefile.bigbootblock.inc
trun
does coreboot excute payload or not?
On Thu, Apr 15, 2010 at 12:15 AM, Chi Min Wang wrote:
> Rudolf Marek wrote:
>
> 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT
freq: 05 VIA HT caps: 0075
00after enable_fid_change
>>>
>>>
>> No other messages after this? Wha
Author: stepan
Date: Wed Apr 14 23:47:24 2010
New Revision: 5438
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5438
Log:
fix COM2 resource bug in fintek f71805f driver.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/superio/fintek/f71805f/superio.c
> > Alternatively you could try if this works:
> >
> > Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> > ===
> > --- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (revision 5411)
> > +++ src/southbridge/nvidia/mcp5
On Tue, Apr 13, 2010 at 12:15:42AM +0200, Stefan Reinauer wrote:
> > Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
> > ===
> > --- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c(revision 5411)
> > +++ src/southb
>
> If we can't decide on the right fix we should leave the warning there as it
> keeps the question open until someone can answer it.
>
I agree.
Thanks,
Myles
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Author: oxygene
Date: Wed Apr 14 22:47:45 2010
New Revision: 5437
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5437
Log:
Quote test -f argument, so it doesn't fail on spaces.
Signed-off-by: Patrick Georgi
Acked-by: Patrick Georgi
Modified:
trunk/Makefile
Modified: trunk/Makefi
Author: oxygene
Date: Wed Apr 14 22:42:42 2010
New Revision: 5436
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5436
Log:
Update mingw source versions and allow parallel builds in buildgcc
Signed-off-by: Patrick Georgi
Acked-by: Patrick Georgi
Modified:
trunk/util/crossgcc/build
On 4/14/10 9:35 PM, Myles Watson wrote:
>
>
> On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer
> mailto:ste...@coresystems.de>> wrote:
>
> On 4/14/10 6:44 PM, Myles Watson wrote:
>>
>> Index: src/northbridge/amd/gx2/chipsetinit.c
>> ==
On 13/04/2010 11:56 PM, Stefan Reinauer wrote:
On 4/14/10 4:18 AM, Dustin Harrison wrote:
I've put several print_info statements in romstage.c and narrowed it
down to the following line in i3100_early_lpc.c:
pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
Further debu
On 14.04.2010 21:35, Myles Watson wrote:
> On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer wrote:
>
>
>> On 4/14/10 6:44 PM, Myles Watson wrote:
>>
>>
>> Index: src/northbridge/amd/gx2/chipsetinit.c
>>
>>> ===
>>> --- src/no
On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer wrote:
> On 4/14/10 6:44 PM, Myles Watson wrote:
>
>
> Index: src/northbridge/amd/gx2/chipsetinit.c
>> ===
>> --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425)
>> +++ src/nort
On 4/14/10 6:44 PM, Myles Watson wrote:
>
> Index: src/northbridge/amd/gx2/chipsetinit.c
> ===
> --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425)
> +++ src/northbridge/amd/gx2/chipsetinit.c (working copy)
>
Author: stepan
Date: Wed Apr 14 20:59:42 2010
New Revision: 5435
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5435
Log:
zero warning days. Move RAMTOP and RAMBASE together.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/Kconfig
trunk/src/arch/i3
Author: stepan
Date: Wed Apr 14 19:18:34 2010
New Revision: 5434
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5434
Log:
fix a case where the fam10 code would overwrite parts of a struct.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/northbridge/am
Author: stepan
Date: Wed Apr 14 19:11:47 2010
New Revision: 5433
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5433
Log:
drop setup_ics code that was blatantly copied from cx700 and
was mainboard specific and unused there already.
some more minor warning fixes.
Signed-off-by: Stefan
Author: myles
Date: Wed Apr 14 18:50:16 2010
New Revision: 5432
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5432
Log:
Remove few more warnings and some dead code.
Signed-off-by: Myles Watson
Acked-by: Myles Watson
Modified:
trunk/src/arch/i386/include/arch/acpi.h
trunk/src/
> Index: src/northbridge/amd/gx2/chipsetinit.c
> ===
> --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425)
> +++ src/northbridge/amd/gx2/chipsetinit.c (working copy)
> @@ -275,7 +275,7 @@
> if ((msr.lo&0xff) == 0x11)
> return;
>
Rudolf Marek wrote:
00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT
freq: 05 VIA HT caps: 0075
00after enable_fid_change
No other messages after this? What was wrong last time?
No more messages,but if I comment the fid/vid related code out(maybe
due to my Sempron 3000 la
Signed-off-by: Stefan Reinauer
Index: src/northbridge/amd/gx2/chipsetinit.c
===
--- src/northbridge/amd/gx2/chipsetinit.c (revision 5425)
+++ src/northbridge/amd/gx2/chipsetinit.c (working copy)
@@ -275,7 +275,7 @@
if ((msr.lo&0xff)
Author: stepan
Date: Wed Apr 14 17:45:02 2010
New Revision: 5430
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5430
Log:
HWHoleSz must be u32...
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c
Modified: trunk/sr
Author: stepan
Date: Wed Apr 14 17:44:21 2010
New Revision: 5429
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5429
Log:
udelay_tsc does not exist in the whole tree.
Neither does quadcore.h (anymore)
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/ma
Hi Keith,
* I also replicated the content of the PIIX4 function 3 config space
after booting with vendor BIOS, as below:
00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02)
00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Author: oxygene
Date: Wed Apr 14 16:41:30 2010
New Revision: 5428
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5428
Log:
sconfig should return success when it's successful
Signed-off-by: Patrick Georgi
Acked-by: Patrick Georgi
Modified:
trunk/util/sconfig/sconfig.tab.c_shipped
Author: oxygene
Date: Wed Apr 14 16:35:40 2010
New Revision: 5427
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5427
Log:
Rename variable to not confuse gcc on mingw
Signed-off-by: Patrick Georgi
Acked-by: Patrick Georgi
Modified:
trunk/util/xcompile/xcompile
Modified: trunk/ut
On Wed, Apr 14, 2010 at 6:50 AM, Stefan Reinauer wrote:
> On 4/14/10 2:36 PM, Myles Watson wrote:
>
> Modified: trunk/src/lib/debug.c
>>
>> ==
>> --- trunk/src/lib/debug.c Wed Apr 14 12:12:23 2010(r5425)
>>
On Wed, Apr 14, 2010 at 5:40 AM, repository service wrote:
> Author: stepan
> Date: Wed Apr 14 13:40:34 2010
> New Revision: 5426
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5426
>
> Log:
> drop quite a lot of dead code that did nothing but produce warnings and
> make
> the rest of
A first attempt at getting epia-en to work
irq table will be total crap.
Mostly (all) stolen from other epia's
Signed-off-by: Jasper Aorangi
epia-en-first-attempt.patch
Description: Binary data
--
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Author: stepan
Date: Wed Apr 14 13:40:34 2010
New Revision: 5426
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5426
Log:
drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reina
Hello,
i845 is on my TODO list. Have patients, the goal is to have it done by
the end of the year.
By the way, this is some what a tricky chipset because it supports both
SDRAM and/or DDR.
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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AMD785G works,
Rudolf
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Author: stepan
Date: Wed Apr 14 12:12:23 2010
New Revision: 5425
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5425
Log:
zero warnings days. Down to under 600 different warnings
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/cpu/amd/model_lx/vsmsetu
Vadim Girlin wrote:
OK, but I sent some disassembled logs - the bios is proprietary, isn't?
Anyway all I want is to say that i don't want to violate any rules.
Any info that I sent was supposed to help the developers.
If some of my posts violates some rules - I'm sorry.
So probably you should say
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5424 to
the coreboot repository. This caused the following
changes:
Change Log:
fix digitallogic adl855pc compilation (and clean up the warnings while at it)
Signed-off-by: Stefan R
Author: stepan
Date: Wed Apr 14 11:04:31 2010
New Revision: 5424
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5424
Log:
fix digitallogic adl855pc compilation (and clean up the warnings while at it)
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/main
Ohh, I thought it was going to be an easy ride, but I'll wait for AMD
785/750 support, as others are very old!
Thanks every one.
On Wed, Apr 14, 2010 at 7:08 AM, Peter Stuge wrote:
> A.Haq Abbad wrote:
> > So you advice me to install coreboot on it?
>
> I wouldn't. You will brick the board.
>
>
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5423 to
the coreboot repository. This caused the following
changes:
Change Log:
move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.
this patch also slight
Author: stepan
Date: Wed Apr 14 09:47:07 2010
New Revision: 5423
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5423
Log:
move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.
this patch also slightly changes it so we have a single cache_as_ram.inc which
require
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