Qing Pei Wang wrote:
does coreboot excute payload or not?
Coreboot says no vaild CBFS header foundBTW,with Sempron 3400(which
support CnQ),coreboot could create ACPI_PSS object correctly,so the
fid/vid related code should check if the CPU is CnQ capable(although it
should be rarely
Author: stepan
Date: Thu Apr 15 10:26:30 2010
New Revision: 5441
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5441
Log:
the dump function assumed that the mbi data comes right after the header.
Which is not (always) the case.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Hi,
I noticed the wiki supported chipsets page has listed under the southbrigde
section AMD RS690 and AMD RS780/RS785?. But RS690 and RS780 are
northbridges, not southbridges, and there is no RS785.
Sorted by codename, the chipsets I can find are*
CodenameProduct Name
Hi,
On 15.04.2010 10:09, dolphinling wrote:
I noticed the wiki supported chipsets page has listed under the
southbrigde section AMD RS690 and AMD RS780/RS785?. But RS690 and
RS780 are northbridges, not southbridges
For AMD CPUs, the northbridge (the chip which hosts the memory
controller) is
I thought we had to wait for GSoC, as it will add support to those mobo's!!!
I can see that AMD has submitted some source code, but I never heard of
anyone who tested it.
regards.
On Wed, Apr 14, 2010 at 11:24 AM, Rudolf Marek r.ma...@assembler.cz wrote:
AMD785G works,
Rudolf
--
coreboot
On 04/15/2010 07:24 AM, A.Haq Abbad wrote:
Ahhh, only if I can help you out.
I can program in C, but looking at coreboot's source code, it makes no
sence to me at all o_O
It is too specialist knowledge I guess.
Sure, two heads are always better than one :-)
No not specialist knowledge, like
Author: stepan
Date: Thu Apr 15 14:41:11 2010
New Revision: 5443
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5443
Log:
don't leave VGA disabled by default on thomson ip1000
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Author: stepan
Date: Thu Apr 15 14:43:07 2010
New Revision: 5444
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5444
Log:
Myles suspected this hangs certain machines, so back it out.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Author: oxygene
Date: Thu Apr 15 16:32:17 2010
New Revision: 5445
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5445
Log:
Avoid two conflicting invocations of build_opt_tbl
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi
following for attachment log, there is no payload was found actually. I
think there is on payload within coreboot.bin. is there a payload.elf in the
coreboot/trunk/ directory?
On Thu, Apr 15, 2010 at 4:17 PM, Chi Min Wang cmw...@ms1.hinet.net wrote:
Qing Pei Wang wrote:
does coreboot excute
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 5445 to
the coreboot repository. This caused the following
changes:
Change Log:
Avoid two conflicting invocations of build_opt_tbl
Signed-off-by: Patrick Georgi
Author: oxygene
Date: Thu Apr 15 16:55:01 2010
New Revision: 5446
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5446
Log:
Avoid strdup(0) in build_opt_tbl
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Modified:
Ticket
Owner
Status
Description
#159 ste...@coresystems.de new Fails to build working ROM for IP1000
#158 ste...@coresystems.de new buildrom svn error
#157 ste...@coresystems.de new utils/inteltool has outdated
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 5446 to
the coreboot repository. This caused the following
changes:
Change Log:
Avoid strdup(0) in build_opt_tbl
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Right. Some board manufacturers call the 785G RS785, and AMD's own
website doesn't have a clear list of which codename corresponds to which
product name. Running a search on AMD's website comes up pretty empty.
OTOH, RS880 is mentioned in the RS780 RPR, so we can assume it works
with the
On Thursday 15 April 2010 17:22:29 Keith Hui wrote:
So realistically how soon can I expect practical RS880/785G support,
if not already? My dev machine/home server/HTPC rocks a Asus
M4A785TD-M EVO with this chipset. I'll assemble a dump later but it
sports, off my head:
Phenom II X4 965
AMD
#159: Fails to build working ROM for IP1000
-+--
Reporter: anonymous | Owner: ste...@…
Type: defect | Status: closed
Priority: major
#158: buildrom svn error
+---
Reporter: vibert vib_...@… | Owner: w...@…
Type: defect |Status: new
Priority: major
#157: utils/inteltool has outdated pciutils check in Makefile
-+--
Reporter: anonymous | Owner: ste...@…
Type: defect | Status: closed
#156: Add Layout File capability to v3 and LAR tool
+---
Reporter: edwin_beas...@… | Owner: hailfinger
Type: enhancement |Status: new
#154: Flashing BIOSes from Fujitsu/Siemens is not supported
---+
Reporter: johannesoberm...@… | Owner:
hailfinger
Type: enhancement |
#152: v3 Geode cs5536 UART2 wrongly configured
+---
Reporter: edwin_beas...@… | Owner: hailfinger
Type: defect |Status: new
#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock
+---
Reporter: edwin_beas...@… | Owner: somebody
Type: enhancement |
#149: AMD DB800 Hangs at Decompressing Coreboot to Ram
+---
Reporter: edwin_beas...@… | Owner: somebody
Type: defect |Status: new
#148: Component defaults to adlo for new tickets in the tracker
+---
Reporter: stuge | Owner: somebody
Type: defect| Status: closed
Priority: minor
#139: flashrom: -c option should be case insensitive
--+-
Reporter: uwe | Owner:
somebody
Type: enhancement | Status:
#129: etherboot payload does not work with HIGH_TABLES
-+--
Reporter: oxygene | Owner: stepan
Type: defect|Status: new
Priority: critical | Milestone:
#108: Add int 10 VESA video driver to libpayload
-+--
Reporter: stuge | Owner: somebody
Type: enhancement| Status: closed
Priority: major | Milestone:
#82: Fix the memory map in coreboot v3
-+--
Reporter: oxygene | Owner: hailfinger
Type: defect|Status: new
Priority: major | Milestone: Setting
#28: Finish Intel 440BX port
-+--
Reporter: uwe| Owner: somebody
Type: task | Status: closed
Priority: critical | Milestone:
On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering vid...@gmail.com wrote:
2010/4/14 Keith Hui buu...@gmail.com
Hi all,
Based on Idwer's RFC I tried adding ACPI to P2B-LS plus completing the
rest of the PIIX4 function 3 initialization.
This is a summary of what I did:
* I used the DSDT
On 14/04/2010 1:14 PM, Dustin Harrison wrote:
I am also in the process of trying my BIOS in the truxton platform,
but it will take me a while to get things up and going. In the
meantime I'm out of ideas on how to narrow this down any further.
I've tried my BIOS build on Truxton to no
On 15.04.2010 18:43, Keith Hui wrote:
On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering vid...@gmail.com wrote:
2010/4/14 Keith Hui buu...@gmail.com
This is also RFC and is not signed off at this point, but comments are
welcome.
When is it okay to sign off :) probably when
On Thu, Apr 15, 2010 at 9:53 AM, Dustin Harrison
dustin.harri...@sutus.com wrote:
I've tried my BIOS build on Truxton to no avail. I get stuck at the same
spot.
Does someone have a reference to an archive of a working Truxton build
directory? At least I can start to compare differences in
On 4/15/10 6:43 PM, Keith Hui wrote:
On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering vid...@gmail.com wrote:
This is also RFC and is not signed off at this point, but comments are
welcome.
When is it okay to sign off :) probably when the major functions like
standby and soft
On Thu, 15 Apr 2010 23:18:32 +0200, Stefan Reinauer ste...@coresystems.de
wrote:
On 4/15/10 6:43 PM, Keith Hui wrote:
On Wed, Apr 14, 2010 at 9:20 PM, Idwer Vollering vid...@gmail.com
wrote:
This is also RFC and is not signed off at this point, but comments are
welcome.
When is
On 4/15/10 11:51 PM, Joseph Smith wrote:
Hmm, So if your code is not quite complete (or not quite ready for commit)
but you think other interested developers might be able to offer help or
suggestions or reviews what do you do then?
Sign it off
--
coresystems GmbH • Brahmsstr. 16 •
On Thu, 15 Apr 2010 23:59:38 +0200, Stefan Reinauer ste...@coresystems.de
wrote:
On 4/15/10 11:51 PM, Joseph Smith wrote:
Hmm, So if your code is not quite complete (or not quite ready for
commit)
but you think other interested developers might be able to offer help or
suggestions or
Author: stepan
Date: Fri Apr 16 01:01:59 2010
New Revision: 5447
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5447
Log:
remove more warnings. move ROOT_COMPLEX selection to fam10
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
On 16.04.2010 00:11, Joseph Smith wrote:
On Thu, 15 Apr 2010 23:59:38 +0200, Stefan Reinauer ste...@coresystems.de
wrote:
On 4/15/10 11:51 PM, Joseph Smith wrote:
Hmm, So if your code is not quite complete (or not quite ready for
commit)
but you think other interested developers
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5448 to
the coreboot repository. This caused the following
changes:
Change Log:
zero warnings days: unify mp tables. fix warnings.
Signed-off-by: Stefan Reinauer
Author: stepan
Date: Fri Apr 16 03:14:50 2010
New Revision: 5449
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5449
Log:
fix up sb600 and it8712f tree.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5449 to
the coreboot repository. This caused the following
changes:
Change Log:
fix up sb600 and it8712f tree.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan
Author: stepan
Date: Fri Apr 16 03:45:44 2010
New Revision: 5450
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5450
Log:
fix romcc compiled i3100 boards.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5450 to
the coreboot repository. This caused the following
changes:
Change Log:
fix romcc compiled i3100 boards.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan
On 15/04/2010 2:18 PM, Ed Swierk wrote:
On Thu, Apr 15, 2010 at 2:04 PM, Dustin Harrison
dustin.harri...@sutus.com wrote:
Yes -- I did the following:
# rm .xcompile
# cd util/crossgcc
# ./buildgcc
# cd ../../
# make clean; make
I also printed out the $(CC) variable in the Makefile to
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