You guys are all crazy, but in a very good way :-)
ron
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Author: stepan
Date: Thu Apr 22 11:22:15 2010
New Revision: 5475
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5475
Log:
fix compilation remaining geode boards
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5475 to
the coreboot repository. This caused the following
changes:
Change Log:
fix compilation remaining geode boards
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by:
Author: stepan
Date: Thu Apr 22 12:44:08 2010
New Revision: 5476
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5476
Log:
None of the cs5536 settings in devicetree.cb were ever used and nobody noticed.
Fix it!
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan
Author: stepan
Date: Thu Apr 22 15:18:09 2010
New Revision: 5477
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5477
Log:
zero warnings days...
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
This patch fixes AHCI mode on i82801g.
By that it also fixes SATA-hotplug on iBASE:MB899
Signed-off-by: Bernhard M. Wiedemann coreboot...@lsmod.de
--
Bernhard M. Wiedemann
software engineer
Index: src/southbridge/intel/i82801gx/i82801gx_sata.c
Author: stepan
Date: Thu Apr 22 20:15:32 2010
New Revision: 5478
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5478
Log:
via epia-m now works with default x86.c instead of its own copy of vgabios.c.
Allows to drop quite a bunch of nasty code
Signed-off-by: Stefan Reinauer
Author: myles
Date: Thu Apr 22 20:16:02 2010
New Revision: 279
URL: http://tracker.coreboot.org/trac/buildrom/changeset/279
Log:
Make a payload only option for buildrom.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson myle...@gmail.com
Modified:
buildrom-devel/Config.in
I did a diff of romstage.inc, using the same codebase (rev 5351) the
only difference between romcc 4051 and 5351 was the timestamp. This is
consistent with my finding that compiling trunk with an older romcc
didn't help the situation.
When I get done with my RAM timing I'll try an svn bisect
Try tracing the original BIOS and coreboot with SerialICE and compare
the differences ... It's a bunch of work but not as ugly as debugging
ROMCC assembler output... :-) http://www.serialice.com/
Stefan
On 22.04.2010, at 20:16, Dustin Harrison dustin.harri...@sutus.com
wrote:
I did a
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Hash: SHA1
Following code does work:
static void bootblock_southbridge_init(void) {
/* ROM decode last 8MB FF80 - on VT8237S/VT8237A */
/* ROM decode last 4MB FFC0 - on VT8237R */
device_t dev;
/* Power management controller */
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Hash: SHA1
Hi again,
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
pci_write_config8(PCI_DEV(0,0x11,0), 0x41, 0x7f);
This code won't make it either. So I suspect it is not good idea
On Sat, Apr 17, 2010 at 2:41 PM, Myles Watson myle...@gmail.com wrote:
This is a reminder to myself in case it is obvious to everyone else:
It seems very difficult to guarantee that the removal/insertion of a
print statement has no other effects.
I printed out the location of a variable,
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Hash: SHA1
Hi again,
Attached patch adds support for tinybootblock on VT8237* to decode whole flash
independent of strapping, making larger flashes work. We cannot walk PCI bus
because HT is not setup yet.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
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Hash: SHA1
Very good idea!
It works!
Attached patch adds support for tinybootblock on VT8237* to decode whole flash
independent of strapping, making larger flashes work. We cannot walk anything
else than PCI bus 0 because HT is not setup yet.
Signed-off-by:
Hi again,
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
pci_write_config8(PCI_DEV(0,0x11,0), 0x41, 0x7f);
This code won't make it either. So I suspect it is not good idea to walk whole
PCI bus so early. Maybe HT
On Tue, 2010-04-20 at 10:42 -0600, Myles Watson wrote:
The issue is that we don't have targets anymore. buildrom probably
needs some update for the coreboot build method.
Yes, buildrom is very much out of date and kconfig does a lot of what
buildrom was doing. It may be time to
Very good idea!
It works!
Great.
Attached patch adds support for tinybootblock on VT8237* to decode whole flash
independent of strapping, making larger flashes work. We cannot walk anything
else than PCI bus 0 because HT is not setup yet.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Author: myles
Date: Fri Apr 23 00:47:29 2010
New Revision: 5479
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5479
Log:
Fix AHCI mode on i82801gx. Fixes SATA hotplug on iBASE:MB899.
Signed-off-by: Bernhard M. Wiedermann coreboot...@lsmod.de
Acked-by: Myles Watson myle...@gmail.com
On Thu, Apr 22, 2010 at 8:33 AM, Bernhard M. Wiedemann
coreboot...@lsmod.de wrote:
This patch fixes AHCI mode on i82801g.
By that it also fixes SATA-hotplug on iBASE:MB899
Signed-off-by: Bernhard M. Wiedemann coreboot...@lsmod.de
Acked-by: Myles Watson myle...@gmail.com
Rev 5479.
Thanks,
On 23.04.2010 03:24, Bao, Zheng wrote:
DDR3 supporting is added.
Very nice, thank you!
I'm sure this will get reviewed quickly.
Regards,
Carl-Daniel
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