Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5507 to
the coreboot repository. This caused the following
changes:
Change Log:
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike th
Hi,
the following sequence might help you to get your tree with local
changes across r5506 and r5507 without too much headache:
svn diff > backup.diff
patch -R -p0 -i backup.diff
svn up
patch -l -p0 -i backup.diff
Please make sure that your local changes don't reintroduce whitespace
(eg. new lin
Am Dienstag, den 27.04.2010, 00:42 +0200 schrieb Anders Jenbo:
> man, 26 04 2010 kl. 16:53 +0200, skrev Stefan Reinauer:
> > On 4/26/10 4:24 PM, Anders Jenbo wrote:
> >
> > > Stefan, since you acked the patch, should I still correct the typos that
> > > Paul pointed out and split it in to a patch
Paul's one is fine so use that.
Mvh Anders
Den 27/04/2010 kl. 09.16 skrev Paul Menzel >:
Am Dienstag, den 27.04.2010, 00:42 +0200 schrieb Anders Jenbo:
man, 26 04 2010 kl. 16:53 +0200, skrev Stefan Reinauer:
On 4/26/10 4:24 PM, Anders Jenbo wrote:
Stefan, since you acked the patch, should
Author: stepan
Date: Tue Apr 27 10:45:30 2010
New Revision: 5508
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5508
Log:
Enable 440BX NB to use large memory modules
Signed-off-by: Anders Jenbo
Signed-off-by: Paul Menzel
Acked-by: Stefan Reinauer
Modified:
trunk/src/northbridge/
Author: oxygene
Date: Tue Apr 27 11:19:47 2010
New Revision: 5509
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5509
Log:
Force mkdir before resolving any make rules.
Signed-off-by: Patrick Georgi
Acked-by: Stefan Reinauer
Modified:
trunk/Makefile
Modified: trunk/Makefile
=
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "oxygene" checked in revision 5509 to
the coreboot repository. This caused the following
changes:
Change Log:
Force mkdir before resolving any make rules.
Signed-off-by: Patrick Georgi
Acked-by: Stefan Reinau
Author: oxygene
Date: Tue Apr 27 11:23:33 2010
New Revision: 5510
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5510
Log:
More "prepare"-dependencies we don't need anymore
Signed-off-by: Patrick Georgi
Acked-by: Patrick Georgi
Modified:
trunk/util/kconfig/Makefile
Modified: tru
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "oxygene" checked in revision 5510 to
the coreboot repository. This caused the following
changes:
Change Log:
More "prepare"-dependencies we don't need anymore
Signed-off-by: Patrick Georgi
Acked-by: Patrick
On 10/16/09 7:33 PM, Myles Watson wrote:
> I think we should clean up memory allocation. There are multiple
> places in the code where RAMTOP is used as an offset into ram and cast
> to a struct.
Maybe that's because the author of that code assumed that this area of
memory would be free to use. An
Anders Jenbo wrote:
> Paul's one is fine so use that.
That's r5508. Thanks!
//Peter
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>> Hello,
>> I want to propose a "coreboot challenge" to first port coreboot to the
>> i840 chpset, second port coreboot to support a very rare i840 dual cpu
>> board, third instead of RAMBUS (which i840 is designed for) this board
>> uses SDRAM. I think this would be a very interesting port for co
On Tue, 27 Apr 2010 10:01:28 -0400, Keith Hui wrote:
>>> Hello,
>>> I want to propose a "coreboot challenge" to first port coreboot to the
>>> i840 chpset, second port coreboot to support a very rare i840 dual cpu
>>> board, third instead of RAMBUS (which i840 is designed for) this board
>>> us
Hi and good morning,
I am new to this coreboot thing. I would like to know
what techniques people are using to avoid bricking their
motherboard the first time they use coreboot (ie, at the
point when a person is completely ignorant about what they
are doing).
I've looked into the IOSS RD1-LPC8 Bi
Joe Korty escribió:
> Hi and good morning,
> I am new to this coreboot thing. I would like to know
> what techniques people are using to avoid bricking their
> motherboard the first time they use coreboot (ie, at the
> point when a person is completely ignorant about what they
> are doing).
>
> I'
Author: myles
Date: Tue Apr 27 17:00:18 2010
New Revision: 5511
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5511
Log:
Enable the cache before initializing the processor name, like model_10 does.
Signed-off-by: Myles Watson
Acked-by: Stefan Reinauer
Modified:
trunk/src/cpu/amd/
On Tue, Apr 27, 2010 at 4:14 AM, Stefan Reinauer wrote:
> On 10/16/09 7:33 PM, Myles Watson wrote:
>
>> I think we should clean up memory allocation. There are multiple places in
>> the code where RAMTOP is used as an offset into ram and cast to a struct.
>
> Maybe that's because the author of th
On Tue, Apr 27, 2010 at 3:59 AM, Stefan Reinauer wrote:
>
> Hi Myles,
>
> http://patchwork.coreboot.org/patch/1209/
>
> Acked-by: Stefan Reinauer
Rev 5511
Thanks,
Myles
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>> Index: cbv2/src/cpu/x86/lapic/lapic_cpu_init.c
>> ===
>> --- cbv2.orig/src/cpu/x86/lapic/lapic_cpu_init.c
>> +++ cbv2/src/cpu/x86/lapic/lapic_cpu_init.c
>> @@ -246,19 +246,15 @@ int start_cpu(device_t cpu)
>> index = ++last_cpu_in
Find or buy a spare flash ROM (you could the one from another board
and back it up so you can restor it when you are done).
Turn on the system, pull out the original ROM and put it some where
safe. Put in your spare and start flashing.
If you ever brick it you can always put the original back i
On Tuesday 27 April 2010 15:55:51 Joe Korty wrote:
Hi Joe
> My motherboard is the H8DME-2 with an 8 MB LPC flash.
You can either buy empty flash chips of the same type and program them
yourself or you can buy already programmed chips from many small shops or on
ebay. (you should also buy such
On Tue, Apr 27, 2010 at 11:50:04AM -0400, ron minnich wrote:
> buy two flash roms. Make two copies of factory bios. Save one
> somewhere really really safe.
>
> Because, sooner or later, you are going to forget and accidentally
> flash over the factory bios, and then you'll be sad.
Yes, very sad:
Just a hint, they don't have to be the same model or even brand.
Mvh Anders
Den 27/04/2010 kl. 17.55 skrev Joe Korty :
On Tue, Apr 27, 2010 at 11:50:04AM -0400, ron minnich wrote:
buy two flash roms. Make two copies of factory bios. Save one
somewhere really really safe.
Because, sooner or l
On 4/27/10 5:37 PM, Myles Watson wrote:
>>> Index: cbv2/src/cpu/x86/lapic/lapic_cpu_init.c
>>> ===
>>> --- cbv2.orig/src/cpu/x86/lapic/lapic_cpu_init.c
>>> +++ cbv2/src/cpu/x86/lapic/lapic_cpu_init.c
>>> @@ -246,19 +246,15 @@ int start
buy two flash roms. Make two copies of factory bios. Save one
somewhere really really safe.
Because, sooner or later, you are going to forget and accidentally
flash over the factory bios, and then you'll be sad.
ron
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> > Sorry, I got interrupted. It was supposed to be:
> > Do we have any multiprocessors that still use CONFIG_RAMBASE < 1M?
> >
> I think we should generally #define RAMBASE for x86 architectures to
> (above) 1MB and remove it from Kconfig.
>
> It will allow us to simplify CAR and make the differ
On Tue, Apr 27, 2010 at 9:27 AM, Myles Watson wrote:
>> > Sorry, I got interrupted. It was supposed to be:
>> > Do we have any multiprocessors that still use CONFIG_RAMBASE < 1M?
>> >
>> I think we should generally #define RAMBASE for x86 architectures to
>> (above) 1MB and remove it from Kconfig
> >> I think we should generally #define RAMBASE for x86 architectures to
> >> (above) 1MB and remove it from Kconfig.
> >>
> >> It will allow us to simplify CAR and make the different CPUs' CAR code
> >> look more alike
> >
> > I think that's a great idea. Extra complexity has never helped us.
>
> is 1M really a prohibitive footprint? I'm just wondering how much we
> kill ourselves on this vs. just taking a "large" amount of memory ...
>
> on a reasonable SMP you're going to have at least 16G
I think that's a good argument for keeping it configurable. We're trying to
support embedded +
Anders Jenbo wrote:
> Just a hint, they don't have to be the same model or even brand.
But make sure that they are compatible. You mentioned that you have
8Mb LPC flash, so some candidates would be:
SST49LF080
Winbond W39V080A (NOTE! not 080FA, which is incompatible)
PMC Pm49FL004T (yes, only 4
On 4/27/10 6:50 PM, Myles Watson wrote:
> For suspend/resume I think we like to keep RAMTOP-RAMBASE = 1M. Last time I
> checked, some of the fam10 boards are using RAMBASE=2M and RAMTOP=16M.
>
> Once you start allowing 48 cores and you want page tables on all of their
> stacks, it gets big quick
> On 4/27/10 6:50 PM, Myles Watson wrote:
> > For suspend/resume I think we like to keep RAMTOP-RAMBASE = 1M. Last
> time I
> > checked, some of the fam10 boards are using RAMBASE=2M and RAMTOP=16M.
> >
> > Once you start allowing 48 cores and you want page tables on all of
> their
> > stacks, it
On Tue, Apr 27, 2010 at 01:38:58PM -0400, Peter Stuge wrote:
> Anders Jenbo wrote:
> > Just a hint, they don't have to be the same model or even brand.
>
> But make sure that they are compatible. You mentioned that you have
> 8Mb LPC flash, so some candidates would be:
>
> SST49LF080
> Winbond W3
Joe Korty wrote:
> > so some candidates would be:
> >
> > SST49LF080
>
> Thanks. The mb shipped with the SST49LF080A and I have
> found that exact part which I just ordered a handful of.
Great! I hope the suffix matches too, I guess it would be -33-4C-NHE.
Sorry, I should have mentioned that. B
Good lock :)
Mvh Anders
Den 27/04/2010 kl. 21.54 skrev Peter Stuge :
Joe Korty wrote:
so some candidates would be:
SST49LF080
Thanks. The mb shipped with the SST49LF080A and I have
found that exact part which I just ordered a handful of.
Great! I hope the suffix matches too, I guess it
Superio is IT8705.
lspci -tvnn
-[:00]-+-00.0 Silicon Integrated Systems [SiS] 630 Host [1039:0630]
+-00.1 Silicon Integrated Systems [SiS] 5513 [IDE] [1039:5513]
+-01.0 Silicon Integrated Systems [SiS] SiS85C503/5513
(LPC Bridge) [1039:0018]
+-01.1 Silicon
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