-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello,
It makes me wonder why CAR on APs use same stack? How does this can work? I
thought CPUs somehow keep caches coherent between them. I see that Fam10h CAR
code allocates 1KB for each AP. But not pre Fam10h.
How this can work?
Rationale for
On 6/6/10 5:01 PM, Rudolf Marek wrote:
Hello,
It makes me wonder why CAR on APs use same stack?
Maybe it is not coherent?
Or maybe it doesn't really work?
I see that Fam10h CAR
code allocates 1KB for each AP. But not pre Fam10h.
How this can work?
Rationale for question is to have some
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
I think it is mostly because there is memory init done by APs. Is this true for
some board?
Thanks,
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
On 6/6/10 5:42 PM, Rudolf Marek wrote:
I think it is mostly because there is memory init done by APs. Is this
true for
some board?
Afaik it's ECC clearing which is implemented several times in the
tree, including stage2.
It needs no PCI access nor console output, though... and parallelizing
the
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Afaik it's ECC clearing which is implemented several times in the
tree, including stage2.
Nope, the APs can init the memory controller too. Check
CONFIG_MEM_TRAIN_SEQ 0 for BSP only
1 = train_ram_on_node is called from init_cpus
2 = dunno - looks
Hey all, I was thinking of trying out coreboot on my old desktop pc and
would like to check whether the motherboard is supported, as it is not in
the list of supported motherboards.
System description:
Board vendor : Gigabyte
Board name : GA-6VX7-4X
CPU : Intel Celeron 633MHz
Northbridge :
On 6/6/10 6:29 PM, Rudolf Marek wrote:
Afaik it's ECC clearing which is implemented several times in the
tree, including stage2.
Nope, the APs can init the memory controller too. Check
CONFIG_MEM_TRAIN_SEQ 0 for BSP only
1 = train_ram_on_node is called from init_cpus
2 = dunno - looks
Hallo David
I am currently working on the chip-set that your board uses. So support is in
progress. I have debug console running via serial and i am about a 1/3 in to
getting the ram initialized. If you think you can help (time is the only real
skill required) coding in the support you are
Hey Anders, thanks for the reply.
Good to hear that progress is being made =] I should have some free
time available in the coming summer holidays, so I'll try to help out
then.
Regarding the rom chip, I got its number (HY29F002TC-90). I'll contact
the flashrom developers about support for it.
I've talked to Marc Jones about this several times over the years.. He
can confirm my memory. There is almost no win to parallelizing any of
the memory or PCI bus setup. Yes, it's supported in the code, kind of,
for some platforms, and maybe it works on some of them, but it's not
worth it and it
Ok that is a Hynix chip, no other chips of that bran is currently supported,
but the data-sheet is available here:
http://www.datasheetcatalog.org/datasheet/hynix/HY29F002TT-55.pdf
So it shouldn't be to much trouble to get it working.
It is a 256KB 5v PLCC32. I think it is parallel but you
Anders Jenbo wrote:
Hynix chip
http://www.datasheetcatalog.org/datasheet/hynix/HY29F002TT-55.pdf
It is a 256KB 5v PLCC32. I think it is parallel
Yep, that's right. LPC and FWH chips are always 3V3, and very rarely
smaller than 4Mbit or 512kbyte.
//Peter
--
coreboot mailing list:
12 matches
Mail list logo
