Hi,
I am working to make a minimal linuxbios without any payload or linux
kernel, I just want to see a nice hello word string on the serial port and
nothing else. is it possible to make such a bios? also to setup only the
necessary HW registers and memory to see the printout message.
how sho
Hej Masoud,
Masoud Fatollahy wrote:
> I am working to make a minimal linuxbios
Note that LinuxBIOS is not really used anymore. The project changed
it's name to coreboot.
> without any payload or linux kernel,
..and *if* LinuxBIOS *is* used, then it refers to coreboot+Linux
kernel as payload.
Masoud Fatollahy wrote:
Hi,
I am working to make a minimal linuxbios without any payload or linux
kernel, I just want to see a nice hello word string on the serial port
and nothing else. is it possible to make such a bios? also to setup only
the necessary HW registers and memory to see the
Daniel,
Daniel J. Celta wrote:
> I wiould have no means to get to that chip and flash it back with
> the original BIOS :(
>
> Is there a way to test if the LinuxBIOS would work, without locking
> myself out...
As you know, coreboot replaces your factory BIOS. So there is no way
You could remove RAM and probably also CPU from the system then, and you
wouldn't need to start the south or north bridge, just the super io.
Just find the first debug message after serial init and change it to what you
want to output.
Mvh Anders
- Reply message -
Fra: "Masoud Fatollah
On Mon, Jul 05, 2010 at 05:02:16PM -0400, Daniel J. Celta wrote:
> Has anyone updated this Supermicro server Board BIOS
> for the H8DME-2..
>
> I have installed FC10, (i was able to complete this
> installation by turning of the RAID configuration in the
> BIOS), and now I am having trouble wh
Hello,
I have Pentium4 laptop motherboard of which BIOS chip is soldered out by
some guys and it doesn't read newly programmed bios chip (a SST49lf080a) as
far as I understand since it even does not beep. And no harddisk signal, no
video and so on. In order to diagnose I have written a VHDL code (
On Tue, 6 Jul 2010 16:50:21 +0300, "r. ozgur doruk"
wrote:
> Hello,
>
> I have Pentium4 laptop motherboard of which BIOS chip is soldered out by
> some guys and it doesn't read newly programmed bios chip (a SST49lf080a)
as
> far as I understand since it even does not beep. And no harddisk sign
Hi,
I can not be sure about that because of
this firmware trap feature of the chipsets I mention. So are those
firmware traps in the SIS chipsets are effective on the boot process of
the processor? Or any other reasons?
I think they are independent of CPU itself. It usually configures some reg
/home/work/coreboot-work/payloads/bayou/build/libpayload/bin/lpgcc -Wall
-Werror -Os -DCONFIG_BUILTIN_LAR -DCONFIG_LZMA -DCONFIG_NRV2B
-I/home/work/coreboot-work/payloads/bayou/build/libpayload/include -c -o
main.o main.c
basename: missing operand
Try `basename --help' for more information.
In fil
hi all,
Since i am trying to do my 780 mass porting, i faced a problem about
Gigabyte dual bios mainboard. my SF100 programmer can not
detect the spi chip unless i removed it from the mainboard, but i can not
use this method to test my coreboot code for i would program
the chip lots of time.
Is
Qing Pei,
Try the flashrom patch here:
http://www.flashrom.org/pipermail/flashrom/2010-April/002905.html
-Bari
Qing Pei Wang wrote:
hi all,
Since i am trying to do my 780 mass porting, i faced a problem about
Gigabyte dual bios mainboard. my SF100 programmer can not
detect the spi chip un
Hi,
Qing Pei Wang wrote:
> i faced a problem about Gigabyte dual bios mainboard. my SF100
> programmer can not detect the spi chip unless i removed it from
> the mainboard,
..
> Is there any idea about this? it's pretty strange about these dual
> bios things.
> Any suggestion will be welcome for m
Ping!?
Could anybody tell me how to proceed?
Peter:did i gave the wrong answers? :)
Thanks,Nils.
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Author: myles
Date: Tue Jul 6 22:36:36 2010
New Revision: 5652
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5652
Log:
A bug fix:
Fix the ctrl_devport_conf_clear to clear the enable bit.
A simplification:
Dynamically enable ck804s that are found instead of relying on #defines.
Removi
These two patches make the SerialICE output match a lot better. I'm
not sure which part is the magic one, but my board works better on a
reset now. I may get around to cleaning it up so that only things
that matter get changed, but it isn't likely to happen very soon.
I'm not suggesting that thi
On Wed, Jun 30, 2010 at 11:52 AM, Edwin Beasant
wrote:
> Seems best of all worlds to me :-)
> Can we get an ack and a commit?
Rev 5653.
Thanks,
Myles
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "myles" checked in revision 5653 to
the coreboot repository. This caused the following
changes:
Change Log:
Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant
Signed-off-by: Myles Watson
Acke
Author: myles
Date: Tue Jul 6 23:37:39 2010
New Revision: 5654
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5654
Log:
Select HAVE_OPTION_TABLE for msi/ms9652_fam10. It fixes the build and doesn't
change the behavior, since it is disabled by default.
Signed-off-by: Myles Watson
Ack
Author: myles
Date: Tue Jul 6 23:40:11 2010
New Revision: 5655
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5655
Log:
Eliminate a couple of warnings from setup_resourcemap.c
Signed-off-by: Myles Watson
Acked-by: Myles Watson
Modified:
trunk/src/northbridge/amd/amdk8/setup_reso
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "myles" checked in revision 5654 to
the coreboot repository. This caused the following
changes:
Change Log:
Select HAVE_OPTION_TABLE for msi/ms9652_fam10. It fixes the build and doesn't
change the behavior, si
hi peter,
there used to have too bios chips, but i remove the B_BIOS, just leave the
M_BIOS which means the main bios .
I am pretty interested with your method. Is that useful for the other
Gigabyte mainboards like my 785GMT-UD2H
On Wed, Jul 7, 2010 at 1:30 AM, Peter Stuge wrote:
> Hi,
>
> Qing
i saw teh method from http://stuge.se/m57sli/ .
i have some questions:
1. U9: Populate flash chip.
2. R509: Remove. (I can not find the from your pic
m57sli_soic_detail_labels.jpg )
3. R89,R130: Populate 0402 100k resistors.
how can i know which register i should move for my own board?
On Wed, J
The Gigabyte 785GMT-UD2H has a fully functional dual SPI flash bios
circuit. Peter's circuit is for boards that leave out one SPI flash
device and you if wish to use a toggle switch to choose between the SPI
flash device you wish to boot from.
The Gigabyte 785GMT-UD2H has everything already so
My chipset is Intel Core2Due/945/ICH7.
I have 3 questions.
First question:
I wonder how PCI memory read cycles can read an instruction from
F000:FFF0 right after reset which is the first instruction of BIOS.
Does Coreboot writes into PCI configuration space of Device 31 of
ICH7-south bridge(LPC
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