Re: [coreboot] amd rs780 gfx lane reversal patch

amd rs789 gfx feature Lane reversal is tested. thanks. Signed-off-by: Kerry She On 8/12/10, Bao, Zheng wrote: > Please add Signed-off-by line in the mail text instead of the > attachment. > > > > feature Lane reversal is tested. > > > > Signed-off-by: Kerry She > > > > > > Index: src/southbrid

Re: [coreboot] amd rs780 gfx lane reversal patch

Please add Signed-off-by line in the mail text instead of the attachment. feature Lane reversal is tested. Signed-off-by: Kerry She Index: src/southbridge/amd/rs780/rs780_gfx.c === --- src/southbridge/amd/rs780/rs780_

Re: [coreboot] Hello and a question.

Votier, Sean (DS-1) wrote: > these chipsets is there some basic legacy I/O mapping for parallel, > serial and other real mode devices by default on power up? Not sure, but I believe not - you usually need to configure that legacy hardware stuff. Maybe some GPIO on the FWH is reachable already ver

Re: [coreboot] Hello and a question.

On Wed, Aug 11, 2010 at 12:15 PM, Votier, Sean (DS-1) wrote: > I’ve been on and off the list for a few months. My email system doesn’t seem > to like list traffic so it’s a bit touch and go so I will have to see how > long it lasts. It’s been interesting reading but now I have a question…. > > I’m

[coreboot] Hello and a question.

Designation: Non-SSA/Finmeccanica I've been on and off the list for a few months. My email system doesn't seem to like list traffic so it's a bit touch and go so I will have to see how long it lasts. It's been interesting reading but now I have a question I'm writing some BIOS code for the

[coreboot] [URGENT] Helpers for FrOSCamp expo needed!

We need helpers for the coreboot/flashrom booth at FrOSCamp! flashrom/coreboot will be exhibiting at the FrOSCamp conference/expo. http://froscamp.org/ - 17/18 September 2010 @ ETH Zurich, Switzerland Admission is free. FrOSCamp is an event similar to FOSDEM, and it will host the FUDCon EMEA and

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

> Ok thank you for all your help. I can boot and run Linux 2.6.33 now and > I see all four CPU cores in /proc/cpuinfo. I compiled and added SeaBIOS > as payload for coreboot and it works. I also compiled and added GPXE to > the image and was able to PXE-boot. However, there are a few problems: >

Re: [coreboot] [patch] DDR3 support of AMD Family 10

bari writes: > "The sr5650 is in the progress. It is about 1 month to go." as Zheng > Bao mentioned. > > It's going to take a few more months to get coreboot up on sr5670 or > sr5690. They definitely will get coreboot support since there are > funded projects for new coreboot mainboard designs usi

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Ok thank you for all your help. I can boot and run Linux 2.6.33 now and I see all four CPU cores in /proc/cpuinfo. I compiled and added SeaBIOS as payload for coreboot and it works. I also compiled and added GPXE to the image and was able to PXE-boot. However, there are a few problems: - The serve

Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support

Hi Donald, David, Yung-Chieh, donald.hu...@ite.com.tw wrote: > Please see the attached file. Thank you very much! I'm very happy that this contribution is now included in superiotool! //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot