Re: [coreboot] [PATCH]USB Host Controller Drivers for libpayload

Good work sofare :) tor, 12 08 2010 kl. 16:35 +0200, skrev Patrick Georgi: > Hi, > > attached patches add support for OHCI (USB1.1 in the non-intel/via > flavor) and xHCI (USB3) to the libpayload USB stack. > > The code is the result of my Google Summer of Code project of this year. > A big "Th

[coreboot] ROMCC help

Hi, I have the following piece of code, and it seems ROMCC can't handle it (offcourse, gcc works): struct bla{ struct bla* next_bla; }; int main(void){return 0;} This is the error message I get while trying to compile it: test.c test.c:2.27: struct bla u

Re: [coreboot] K8 SMP broken?

Anyone feeling guilty? ;-) Is it pre fam10h? It was always big mystery for me how it can work ;) The AP got the SAME stack... If you don't believe check for yourself. I think simple fix would be to do same thing as FAM10h code is doing. Please can you try attached patch? Dunno if it works lo

[coreboot] global variables in romstage

Hi, I was told about an issue with our romstage handling, as the linker happily links in global variables (with addresses in ROM). That obviously doesn't work for writable values, but is a silent error (until things _really_ go wrong on runtime), so I looked for a way to break coreboot at build t

Re: [coreboot] [PATCH]USB Host Controller Drivers for libpayload

Patrick Georgi wrote: > attached patches add support for OHCI (USB1.1 in the non-intel/via > flavor) and xHCI (USB3) to the libpayload USB stack. .. > Signed-off-by: Patrick Georgi Good stuff! Acked-by: Peter Stuge -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailma

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

BTW: It would be easier for me to see what was going on if we could pass back and forth patches to the tree that apply to the s2881's directory. Then when we're ready to commit there will be a lot less to review. Here's one way to do that: svn cp src/mainboard/tyan/s2881 src/mainboard/hp/dl145

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

> Myles Watson wrote: > > > > > >> Ok thank you for all your help. I can boot and run Linux 2.6.33 now and > >> I see all four CPU cores in /proc/cpuinfo. I compiled and added SeaBIOS > >> as payload for coreboot and it works. I also compiled and added GPXE to > >> the image and was able to PXE-boo

Re: [coreboot] K8 SMP broken?

> has anybody tested K8 SMP recently? In this thread: Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ? Oskar is testing K8 SMP. It seems to work for him. He's basing his port off the s2881. Maybe you could compare the s2881 and s2885 code. Thanks, Myles -- coreboot mailing

Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?

Myles Watson wrote: > > >> Ok thank you for all your help. I can boot and run Linux 2.6.33 now and >> I see all four CPU cores in /proc/cpuinfo. I compiled and added SeaBIOS >> as payload for coreboot and it works. I also compiled and added GPXE to >> the image and was able to PXE-boot. Howeve

[coreboot] K8 SMP broken?

Hi all, has anybody tested K8 SMP recently? I've built r5689 for a Tyan Thunder K8W (s2885, dual socket 940), but it hangs. Commenting out allow_all_aps_stop(bsp_apicid) brings it up, but with a single CPU. Anyone feeling guilty? ;-) Torsten -- coreboot mailing list: coreboot@coreboot.