On 11/21/10 3:39 PM, Rudolf Marek wrote:
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc
is read from NVRAM. Why you ask? Because we cannot do it as on intel,
because the framebuffer might be there
On 11/21/10 3:37 PM, Uwe Hermann wrote:
i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register pressure on romcc
chipsets. We did the same conversion on i440BX, i830, and others.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Stefan
Author: stepan
Date: Mon Nov 22 09:09:50 2010
New Revision: 6111
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6111
Log:
Printing coreboot debug messages on VGA console is pretty much useless, since
initializing VGA happens pretty much as the last thing before starting the
payload.
On 11/21/10 11:55 PM, Qing Pei Wang wrote:
agree, actually the vga will show nothing about the booting message,
it's too fast.
Acked-by: QingPei Wangwangqing...@gmail.com
mailto:wangqing...@gmail.com
Thanks, Qing Pei, committed as r6111!
Stefan
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coreboot mailing list: coreboot@coreboot.org
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 6111 to
the coreboot repository. This caused the following
changes:
Change Log:
Printing coreboot debug messages on VGA console is pretty much useless, since
initializing VGA happens
Author: uwe
Date: Mon Nov 22 13:59:36 2010
New Revision: 6112
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6112
Log:
i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register pressure on romcc
chipsets. We did the same conversion on
Author: oxygene
Date: Mon Nov 22 14:07:10 2010
New Revision: 6113
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6113
Log:
Workaround to get die.c to work with romcc.
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Acked-by: Patrick Georgi patr...@georgi-clan.de
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer uwe checked in revision 6112 to
the coreboot repository. This caused the following
changes:
Change Log:
i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6113 to
the coreboot repository. This caused the following
changes:
Change Log:
Workaround to get die.c to work with romcc.
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Author: oxygene
Date: Mon Nov 22 15:14:56 2010
New Revision: 6114
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6114
Log:
Final set of smp_write_bus - mptable_write_buses changes.
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Acked-by: Patrick Georgi patr...@georgi-clan.de
Hi,
with r6114, no board in trunk uses smp_write_bus directly anymore.
Instead, mptable_write_buses looks up all buses in the device tree and
adds them to the table accordingly.
I propose to hide smp_write_bus, so no new board can reintroduce such code.
==
Make smp_write_bus static (local
With low serial console loglevels a pcie graphics card is not
initialized properly because the pcie link takes some time to come
up.
I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
and higher only boot looks like on my system (with pcie printks set
to BIOS_ERR so they show
On Mon, Nov 22, 2010 at 03:20:20PM +0100, Patrick Georgi wrote:
Hi,
with r6114, no board in trunk uses smp_write_bus directly anymore.
Instead, mptable_write_buses looks up all buses in the device tree and
adds them to the table accordingly.
Awesome!
I propose to hide smp_write_bus, so
Ticket
Owner
Status
Description
#168 ste...@coresystems.de new USBDEBUG might slow down coreboot
#162 oxygene new Move SYSTEM_TYPE to Kconfig
#160 oxygene new Build system: There's no convincing CFLAGS
Author: uwe
Date: Mon Nov 22 16:57:57 2010
New Revision: 6115
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6115
Log:
Drop per-board ram_check() calls for now.
Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only
Author: uwe
Date: Mon Nov 22 17:23:54 2010
New Revision: 6116
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6116
Log:
Drop unused ACPI_WRITE_MADT_IOAPIC #define.
This should probably be C code in some .c file anyway.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe
On Wed, Oct 27, 2010 at 08:50:19PM +, Jonathan A. Kollasch wrote:
Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by
default on all boards) into Kconfig.
For bookkeeping: An updated patch has been committed as r6109.
Uwe.
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http://hermann-uwe.de | http://sigrok.org
On Sun, Oct 24, 2010 at 03:27:33PM +0200, Uwe Hermann wrote:
On Mon, Oct 11, 2010 at 09:24:07PM +0200, Peter Stuge wrote:
Uwe Hermann wrote:
Factor out a few commonly duplicated functions from northbridge.c.
The following functions are moved to devices/device_util.c:
-
The diff to that in the K8 version is this (in tolm_test()):
- if (!best || (best-base new-base))
+ /* Skip VGA. */
+ if (!best || (best-base new-base new-base 0xa)) {
Small fix which could also be moved into the global tolm_test(). Depending on
whether or not
* repository service s...@coreboot.org [101122 14:07]:
Author: oxygene
Date: Mon Nov 22 14:07:10 2010
New Revision: 6113
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6113
Log:
Workaround to get die.c to work with romcc.
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
* Bao, Zheng zheng@amd.com [101122 09:02]:
But there would be nothing on the screen if no payload is attached. That would
be confusing when the board is still in debug stage.
We might want to add an exception for this.
However, if the board is still in debug stage, a debug console (serial
Am 22.11.2010 19:32, schrieb Stefan Reinauer:
Didn't we add attribute((noreturn)) (fake) support
to romcc at some point?
There is _some_ support, but it's rather fragile, and I didn't find the
correct incantation immediately, so I opted to drop it for now.
Patrick
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coreboot mailing list:
Author: ruik
Date: Mon Nov 22 23:00:52 2010
New Revision: 6117
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6117
Log:
1) wraps the s3 parts of chipset code/memory init code with if
CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
2) the patch implements
Can't we read the size of the framebuffer on resume? Maybe the register
is connected to the resume power well?
Nope it is not, and if we have a CMOS option for FB size we don't know how big
it is. This solution is therefore most easy and straightforward.
Committed revision 6117.
Thanks,
-Original Message-
From: Liu Tao [mailto:liutao1...@gmail.com]
Sent: Monday, November 22, 2010 04:50 AM
To: coreboot@coreboot.org
Cc: Scott Duplichan; mrta...@gmail.com; wangqing...@gmail.com; zheng@amd.com
Subject: K8+RS780+SB710 board failed to boot linux with 4G DRAM
Hello all,
Author: oxygene
Date: Tue Nov 23 08:19:54 2010
New Revision: 6118
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6118
Log:
Make smp_write_bus static (local scope), to prevent new boards from
using it directly again.
Signed-off-by: Patrick Georgi patr...@georgi-clan.de
Acked-by: Uwe
Author: oxygene
Date: Tue Nov 23 08:30:50 2010
New Revision: 6119
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6119
Log:
USBDEBUG by default in abuild was committed by mistake and
then left in because USBDEBUG was actively worked on.
This isn't true anymore, so drop it
Hi,
right now, the build system assumes that .config is in $(top). abuild
stores each board's .config by copying it into the build directory after
the fact, while clobbering any existing files.
With the attached patch, it's possible to define a new location for
.config, using the DOTCONFIG
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