Author: stepan
Date: Mon Nov 29 01:20:20 2010
New Revision: 6130
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6130
Log:
fix typo
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c
Modified: trunk/src/southbridge
On 11/28/10 12:47 PM, Idwer Vollering wrote:
> 2010/11/28 Uwe Hermann mailto:u...@hermann-uwe.de>>
>
> On Sat, Nov 27, 2010 at 12:02:46PM +0100, Tobias Diedrich wrote:
> > Add acpi_is_wakeup_early to i82371eb and P2B.
> > Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
> > Al
On 11/28/10 12:36 PM, Uwe Hermann wrote:
> On Sat, Nov 27, 2010 at 12:02:46PM +0100, Tobias Diedrich wrote:
>> Add acpi_is_wakeup_early to i82371eb and P2B.
>> Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
>> Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
>> uses the same acpi
2010/11/28 Uwe Hermann
> On Sat, Nov 27, 2010 at 12:02:46PM +0100, Tobias Diedrich wrote:
> > Add acpi_is_wakeup_early to i82371eb and P2B.
> > Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
> > Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
> > uses the same acpi wakeup vecto
On Sat, Nov 27, 2010 at 12:02:46PM +0100, Tobias Diedrich wrote:
> Add acpi_is_wakeup_early to i82371eb and P2B.
> Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
> Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
> uses the same acpi wakeup vector as S3.
> Other chipsets so far on
On Sun, Nov 28, 2010 at 12:06:56PM +0100, Tobias Diedrich wrote:
> BTW, my first idea was to use an acpi method that looks up pmbase in
> the pci cfg space, but when I define a method like this:
>
> Method(TEST, 2)
> {
> Return (Add(Arg0, Arg1))
> }
>
> I g
#170: Need coreboot for ASUS P4PE_X/SE
--+---
Reporter: a...@… | Owner: ste...@…
Type: defect |Status: new
Priority: major | Milestone:
Component: coreboot | Keywords: core
Author: uwe
Date: Sun Nov 28 15:24:07 2010
New Revision: 6129
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6129
Log:
devicetree.cb: Only add as many entries as there are DIMM slots.
Signed-off-by: Uwe Hermann
Acked-by: Uwe Hermann
Modified:
trunk/src/mainboard/asus/a8n_e/device
Tobias Diedrich wrote:
> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU S
Stefan Reinauer wrote:
> On 11/27/10 1:40 AM, repository service wrote:
> > +++ trunk/src/mainboard/asus/p2b/dsdt.asl Sat Nov 27 10:40:16 2010
> > (r6127)
> > @@ -0,0 +1,101 @@
> ...
> > +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
> > +{
> > + /* Define the main pr
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