Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6198 to
the coreboot repository. This caused the following
changes:
Change Log:
Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.
Compiles, but not boot
On Fri, Dec 17, 2010 at 8:19 PM, Patrick Georgi
patrick.geo...@coresystems.de wrote:
Hi,
attached to this mail you'll find support for the Intel Poulsbo chipset, the
first iteration of their System Controller Hub (SCH) designs that integrate
northbridge and southbridge into a single chip.
Hi again,
Well the lock survives all resets except power on.
Yes, and that might be a bug in how we keep state across resets.
Also, we were trying to initialize SMM several times on each boot, once
per CPU and then once in the southbridge code. So you should actually
have seen this message
Hi,
OK, here are fixes on top of your patch to make it work again ;)
It seems you missed my change of bit6 any idea why?
+ southbridge_smi_cmd, // [6]
We don't need Aclose either - this is for access to videoRAM for example (but
our data can reside in Aseg... so we dont want
Author: oxygene
Date: Sat Dec 18 12:55:06 2010
New Revision: 6199
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6199
Log:
A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6199 to
the coreboot repository. This caused the following
changes:
Change Log:
A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it
On Sat, Dec 18, 2010 at 02:19:48AM +0100, Patrick Georgi wrote:
attached to this mail you'll find support for the Intel Poulsbo chipset, the
first iteration of their System Controller Hub (SCH) designs that integrate
northbridge and southbridge into a single chip.
Great stuff, thanks a lot!
On 12/18/10 6:01 AM, Tadas S wrote:
I have inserted USB2.0 pci extension card to msi ms6119 mainboard.
The problems appear when I try to boot from USB flash drive attached
to that controller. If coreboot detects that controller as EHCI, the
boot fails just at FILO.
If coreboot detects it as
Am Samstag, 18. Dezember 2010, um 11:00:30 schrieb Stefan Reinauer:
Is busmastering enabled on your EHCI controller?
should happen in libpayload/drivers/usb/usbinit.c
Patrick
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Author: stepan
Date: Sun Dec 19 00:29:37 2010
New Revision: 6201
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6201
Log:
SMM for AMD K8 Part 1/2
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Added:
trunk/src/cpu/amd/smm/
Author: stepan
Date: Sun Dec 19 00:30:59 2010
New Revision: 6202
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6202
Log:
SMM on AMD K8 Part 2/2
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
Author: uwe
Date: Sun Dec 19 02:08:40 2010
New Revision: 6203
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6203
Log:
ASUS M2N-E: Enable PCI-E x16 slot.
Simple devicetree.cb fix, tested on hardware using a PCI-E x16 graphics card.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
See patch
The same mechanisms are used for normal and fallback images.
Hence drop the FALLBACK_ prefix
Signed-off-by: Stefan Reinauer ste...@coreboot.org
Index: src/Kconfig
===
--- src/Kconfig (revision 6203)
+++ src/Kconfig
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