Nils wrote:
> Patrick:
> Thanks for the quick ack.
>
> All:
> It would be nice if someone with SVN access would be able to commit
> these patches.
I've now committed 1,2,5 and 6. Please help me understand 3,4 better.
//Peter
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Nils wrote:
> Move VIDEO_MB to Kconfig.
> +++ src/northbridge/amd/gx2/Kconfig (working copy)
> @@ -21,6 +21,11 @@
> bool
> select GEODE_VSA
>
> +config VIDEO_MB
> + int
> + default 8
> + depends on NORTHBRIDGE_AMD_GX2
> +
Acked-by: Peter Stuge
r6211
But only on the
Author: stuge
Date: Sun Dec 26 06:24:50 2010
New Revision: 6211
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6211
Log:
Move Geode GX2 UMA video memory size to Kconfig
Signed-off-by: Nils Jacobs
Acked-by: Patrick Georgi
Acked-by: Peter Stuge
Modified:
trunk/src/northbridge/amd/
Nils wrote:
> Delete some unused code.
>
> Signed-off-by: Nils Jacobs
Acked-by: Peter Stuge
r6210
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Author: stuge
Date: Sun Dec 26 06:21:18 2010
New Revision: 6210
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6210
Log:
Remove dead and unused Geode GX2 code
Signed-off-by: Nils Jacobs
Acked-by: Patrick Georgi
Acked-by: Peter Stuge
Modified:
trunk/src/cpu/amd/model_gx2/cpuregin
Nils wrote:
> - __asm__ __volatile__("hlt\n");
> + while(1) {
> + __asm__ __volatile__("hlt\n");
> + }
Why not call die() instead? Is it too early for that?
//Peter
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Nils wrote:
> Replace some MSR register numbers with names.
>
> Signed-off-by: Nils Jacobs
Acked-by: Peter Stuge
r6209
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Author: stuge
Date: Sun Dec 26 06:16:47 2010
New Revision: 6209
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6209
Log:
Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs
Acked-by: Patrick Georgi
Acked-by: Peter Stuge
Modified:
trunk/src/cpu
Nils wrote:
> -Clean up some comments.
> -Remove some white spaces.
> -Some coding style fixes.
>
> Signed-off-by: Nils Jacobs
Acked-by: Peter Stuge
r6208
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Nils wrote:
> Remove wrong GX2 processor IIOC mode setting on CS5535 southbridge
> code and fix CIS mode comments.
Hm, please talk a little about this?
> +++ src/southbridge/amd/cs5535/early_setup.c (working copy)
> @@ -107,15 +107,11 @@
..
> - //Only do this if we are building for 5535
> -
Patrick:
Thanks for the quick ack.
All:
It would be nice if someone with SVN access would be able to commit these
patches.
Thanks, Nils.
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On Sat, Dec 25, 2010 at 12:21:35PM +0100, Marc Bertens wrote:
> hi all,
>
> i restarted the my project with the nokia IP530, and checked out the
> newest release of coreboot and i got only to the initstage of the
> i440bx. I changed my Kconfig and added SDRAMPWR_4DIMM for safety, but
> not change
Author: uwe
Date: Sat Dec 25 23:54:41 2010
New Revision: 6207
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6207
Log:
Nokia IP530: Add missing "select SDRAMPWR_4DIMM".
This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one).
Thanks Marc Bertens for bringing up
Hi all,
This is RFC patch. It adds support for automatic PSS object generation for AMD
pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite
during one particularly boring flight. Too pity it is only for Opteron CPUs.
Someone needs to finish the second PDF for All ot
hi all,
i restarted the my project with the nokia IP530, and checked out the
newest release of coreboot and i got only to the initstage of the
i440bx. I changed my Kconfig and added SDRAMPWR_4DIMM for safety, but
not change in the startup it stays the same.
Anyone any ideas ?
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