I'm sure the problem is coming from PIRQ map; needs some fine tuning. The
board has four serials and all of them are connected the 81216DG super IO
chip so I'm using the first serial port, the onchip uarts are disabled.
There is an additional hwmon chip(f71858) which I did not touched
yet.
Author: zbao
Date: Tue Jan 18 10:29:19 2011
New Revision: 6261
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6261
Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Deleted:
trunk/src/vendorcode/
Author: zbao
Date: Tue Jan 18 10:31:29 2011
New Revision: 6262
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6262
Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Deleted:
Author: zbao
Date: Tue Jan 18 10:32:15 2011
New Revision: 6263
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6263
Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Deleted:
Author: zbao
Date: Tue Jan 18 10:34:31 2011
New Revision: 6264
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6264
Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Modified:
Author: zbao
Date: Tue Jan 18 10:36:44 2011
New Revision: 6265
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6265
Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Modified:
trunk/Makefile
Hi all,
Well for all those Europeans which might feel bit sad that California is far
far way I have a following proposal.
Lets meet in Prague for a weekend in April/May. I think I could get some
dormitory style accommodation and we can meet at university at the weekend.
Prague is not so
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer zbao checked in revision 6261 to
the coreboot repository. This caused the following
changes:
Change Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer zbao checked in revision 6262 to
the coreboot repository. This caused the following
changes:
Change Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by:
Rudolf Marek wrote:
Well for all those Europeans which might feel bit sad that
California is far far way I have a following proposal.
Lets meet in Prague for a weekend in April/May.
These are really awesome initiatives! I wish I could come to both,
but I guess it'll be Prague for me.
In any
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer zbao checked in revision 6263 to
the coreboot repository. This caused the following
changes:
Change Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer zbao checked in revision 6264 to
the coreboot repository. This caused the following
changes:
Change Log:
remove the code which is not ready to release.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by:
Author: oxygene
Date: Tue Jan 18 13:12:47 2011
New Revision: 6266
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6266
Log:
Eliminate strict aliasing related warnings.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer ste...@coreboot.org
Modified:
Author: oxygene
Date: Tue Jan 18 13:14:08 2011
New Revision: 6267
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6267
Log:
Remove overengineering, part 1/many
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Patrick Georgi patrick.geo...@secunet.com
Modified:
Am Dienstag, den 18.01.2011, 13:52 +0100 schrieb Mathias Krause:
+ if (option_table) {
+ struct lb_record *rec_dest = lb_new_record(head);
+ /* Copy the option config table, it's already a
lb_record... */
+ memcpy(rec_dest,
On 14.01.2011 11:39, Patrick Georgi wrote:
Hi,
currently the option table (which contains the metadata necessary to
parse CMOS data properly) is stored in ramstage. This patch moves it to
CBFS, making it available for inspection by utilities.
The idea is to allow nvramtool to configure
Author: oxygene
Date: Tue Jan 18 14:56:36 2011
New Revision: 6268
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6268
Log:
Move option table (cmos.layout's binary representation)
to CBFS and adapt coreboot to use it.
Comments by Stefan and Mathias taken into account (except for
the
Am Dienstag, den 18.01.2011, 14:17 +0100 schrieb Patrick Georgi:
I guess TMPFILE_LEN used to work because it usually ends up as a short
name in /tmp/, 20 characters or less. But you're right, this needs
fixing.
Actually I'm mistaken on that - it's a relative path (but outside /tmp),
which
On 18.01.2011 14:17, Patrick Georgi wrote:
Am Dienstag, den 18.01.2011, 13:52 +0100 schrieb Mathias Krause:
+ if (option_table) {
+ struct lb_record *rec_dest = lb_new_record(head);
+ /* Copy the option config table, it's already a
lb_record...
Author: oxygene
Date: Tue Jan 18 15:28:45 2011
New Revision: 6269
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6269
Log:
Report if cmos_layout.bin can't be found when it should.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Patrick Georgi
Author: oxygene
Date: Tue Jan 18 15:38:59 2011
New Revision: 6270
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6270
Log:
Fix fwrite tests.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Patrick Georgi patrick.geo...@secunet.com
Modified:
Patrick Georgi wrote:
+ if(!fwrite(cmos_table, (int)(ct-size-1), 1, fp)) {
It would be better to check that all bytes have been written not only
some, so do something like:
if(fwrite(cmos_table, (int)(ct-size-1), 1, fp) != ct-size-1) {
fwrite returns the number of
Hello Frank,
Please can you have a look into this thread to see what it has brought.
Nice would be to get answers for questions regarding the redistribution of
ROMs/Firmware.
Additionally I would like to consult some undocumented bit which is documented
in SB600 but not SB710. Maybe it is a
Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
This patch is buid and boot tested.
Hi Peter,
You wrote:
+config VIDEO_MB
+ int
+ default 8
+ depends on NORTHBRIDGE_AMD_GX2
+
Acked-by: Peter Stuge peter at stuge.se
Auf 18.01.2011 11:09, Peter Stuge schrieb:
Rudolf Marek wrote:
Well for all those Europeans which might feel bit sad that
California is far far way I have a following proposal.
Lets meet in Prague for a weekend in April/May.
Good idea! I'm not yet 100% sure whether I will have time to
Carl-Daniel Hailfinger wrote:
At LinuxTag there are usually more people interested in using
coreboot than developing, but there are exceptions, and it would be
great to invite those who are interested to the hackathon.
We could ask for a hack room at LinuxTag. Maybe we'll even get one.
Author: stepan
Date: Wed Jan 19 07:31:24 2011
New Revision: 6271
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6271
Log:
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Author: stepan
Date: Wed Jan 19 07:32:35 2011
New Revision: 6272
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6272
Log:
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg. This reduces boot time by
about 1 second on
repository service wrote:
Log:
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Signed-off-by: Kevin O'Connor ke...@koconnor.net
Acked-by: Stefan Reinauer ste...@coreboot.org
* Sven Schnelle sv...@stackframe.org [110117 21:46]:
Index: src/ec/acpi/ec.h
===
--- src/ec/acpi/ec.h (revision 0)
+++ src/ec/acpi/ec.h (working copy)
@@ -17,9 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor,
* Peter Stuge pe...@stuge.se [110117 03:25]:
repository service wrote:
+++ trunk/src/pc80/mc146818rtc_early.c Fri Jan 14 08:40:24 2011
(r6253)
..
static inline int do_normal_boot(void)
{
+ char *cmos_default = cbfs_find_file(cmos.default, 0xaa);
unsigned char
* Peter Stuge pe...@stuge.se [110119 07:37]:
repository service wrote:
Log:
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Signed-off-by: Kevin O'Connor
Author: stepan
Date: Wed Jan 19 07:54:42 2011
New Revision: 6273
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6273
Log:
Revert r5902 to make code more readable again. At least three people like to
have this go away again.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Sven Schnelle wrote:
+++ src/ec/acpi/Makefile.inc (revision 0)
@@ -0,0 +1 @@
+driver-y += ec.c
..
+++ src/mainboard/roda/rk886ex/Makefile.inc (working copy)
@@ -18,7 +18,6 @@
##
ramstage-y += m3885.c
-ramstage-y += ec.c
driver-y += rtl8168.c
smm-$(CONFIG_HAVE_SMI_HANDLER)
Author: stepan
Date: Wed Jan 19 07:56:33 2011
New Revision: 6274
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6274
Log:
Add Geode GX2 memmory descriptors.
Add a simple README file.
* Nils njaco...@hetnet.nl [110113 15:42]:
Add Geode GX2 memmory descriptors.
Add a simple README file.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Thanks, Nils.
Thanks, r6274
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
* Nils njaco...@hetnet.nl [110113 16:19]:
Hello all,
In the past i used coreboot without a VGAbios and used the linux framebuffer
driver and that works ok.
I am trying to get onboard early VGA running on my Geode GX2 board but until
now i have no succes.( the screen stays black until the
* Alex G. mr.nuke...@gmail.com [110114 16:37]:
Added preliminary support for the ASUS K8V-X SE and the VIA K8T800
chipset. Coreboot is able to finalize and load SeaBIOS, which boots from
IDE HDD or DVD. IRQ ACPI and MP tables are not yet complete.
Signed-off-by: Alexandru Gagniuc
* Bao, Zheng zheng@amd.com [110111 03:19]:
I personally like this patch, not because I did. It is easy to use and
handle. I am gonna signed-off-by it. If I get support, I will check it in.
Zheng
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan Reinauer ste...@coreboot.org
* Snoke sn...@iki.fi [110109 20:07]:
Serial port 2 won't work on Epia-Mii.
Following patch I get it work.
Found solution at Linuxbios archive : [LinuxBIOS] EPIA M COM2 problem +
possible solution?
--- coreboot/src/superio/via/vt1211/vt1211.c 2011-01-09 16:05:47.0
+0200
+++
Nils wrote:
Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
This patch is buid and boot tested.
Hi Peter,
You wrote:
+config VIDEO_MB
+ int
+ default 8
+ depends on NORTHBRIDGE_AMD_GX2
+
Acked-by: Peter
* Peter Stuge pe...@stuge.se [110119 07:55]:
Sven Schnelle wrote:
+++ src/ec/acpi/Makefile.inc(revision 0)
@@ -0,0 +1 @@
+driver-y += ec.c
..
+++ src/mainboard/roda/rk886ex/Makefile.inc (working copy)
@@ -18,7 +18,6 @@
##
ramstage-y += m3885.c
-ramstage-y +=
* Stefan Reinauer stefan.reina...@coreboot.org [110119 07:37]:
* Peter Stuge pe...@stuge.se [110117 03:25]:
repository service wrote:
+++ trunk/src/pc80/mc146818rtc_early.cFri Jan 14 08:40:24 2011
(r6253)
..
static inline int do_normal_boot(void)
{
+ char
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