Hey guys,
attached is a patch to add support for the IT8720F Super I/O to superiotool.
There are three NANA bits in the GPIO reset part, the first two of those
were unclear to me so I added them as NANA.
One with more experience than me could/should take a look at those
please but it should be
Hi,
This patch tells nvramtool about another place where it can find
information about the CMOS checksum location and range before it reverts
to its own default values.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
--
Patrick Georgi
SINA-Development - High Security
secunet Security
Hi,
in preparation of teaching nvramtool to edit files instead of real
hardware, this patch abstracts CMOS accesses a bit more.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
--
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760
Attached patch allows nvramtool to work on in-memory data.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
--
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 -
This is the first patch of this series that actually adds a new feature.
Use nvramtool -C to work on CBFS images that contain cmos_layout.bin for
CMOS metadata and cmos.default for CMOS defaults.
Read/Write/Enum on CMOS data work on cmos.default then.
Signed-off-by: Patrick Georgi
This patch adds a -D option to tell nvramtool to work on data in a plain
CMOS image (as extracted by the nvramtool dump option, for example).
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
--
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG -
* Christian Ruppert id...@gentoo.org [110120 13:48]:
Hey guys,
attached is a patch to add support for the IT8720F Super I/O to superiotool.
There are three NANA bits in the GPIO reset part, the first two of those
were unclear to me so I added them as NANA.
One with more experience than
* Georgi, Patrick patrick.geo...@secunet.com [110120 14:34]:
Hi,
in preparation of teaching nvramtool to edit files instead of real
hardware, this patch abstracts CMOS accesses a bit more.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Signed-off-by: Stefan Reinauer
* Georgi, Patrick patrick.geo...@secunet.com [110120 14:35]:
Attached patch allows nvramtool to work on in-memory data.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer ste...@coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
* Georgi, Patrick patrick.geo...@secunet.com [110120 14:36]:
This is the first patch of this series that actually adds a new feature.
Use nvramtool -C to work on CBFS images that contain cmos_layout.bin for
CMOS metadata and cmos.default for CMOS defaults.
Read/Write/Enum on CMOS data work on
* Georgi, Patrick patrick.geo...@secunet.com [110120 14:38]:
This patch adds a -D option to tell nvramtool to work on data in a plain
CMOS image (as extracted by the nvramtool dump option, for example).
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Nice work!
Acked-by: Stefan
Dear Patrick,
skimming through you patch I noticed a few things.
Am Donnerstag, den 20.01.2011, 14:36 +0100 schrieb Georgi, Patrick:
[…]
+ * Copyright (C) 2008, Jordan Crouse jor...@cosmicpenguin.net
THe colon after »2008« should be deleted.
+ * Copyright (C) 2011 secunet Security
* Georgi, Patrick patrick.geo...@secunet.com [110120 14:31]:
Hi,
This patch tells nvramtool about another place where it can find
information about the CMOS checksum location and range before it reverts
to its own default values.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
I investigated this some more and i think i found the problem.
The crosscompiler is working ok now and my coreboot rom has the same size as
the one from the automatic build system of coreboot.org exept for the SeaBios
payload mine is 46881 bytes and the one from the automatic build system of
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Nils
Sent: Thursday, January 20, 2011 05:00 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] abuild error
]I investigated this some more and i think i found the problem.
]The
Op vrijdag 21 januari 2011 01:26:06 schreef u:
Thanks for investigating. I have always used the same xgcc for coreboot and
seabios. I suppose your newly built xgcc is version 4.5.2. Is there any
chance the coreboot.org build system is not yet using 4.5.2, and that
explains the size
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Nils
Sent: Thursday, January 20, 2011 07:18 PM
To: coreboot@coreboot.org
Subject: Re: [coreboot] abuild error
]Thanks for your answer.
]Which coreboot revision and board did you
I built r6275 for my RS690/SB600 based box with debug level 8.
This box did not boot up.
The last displayed console message is `bsp_apicid=0x`.
This happens line 269 at src/console/vtxprintf.c.
...
num = va_arg(args, unsigned int);
...
I moved this source tree to ubuntu 9.0.4_x86_64 box.
* Yoo, Taik-Yon jaa...@gmail.com [110121 03:39]:
I built r6275 for my RS690/SB600 based box with debug level 8.
This box did not boot up.
The last displayed console message is `bsp_apicid=0x`.
This happens line 269 at src/console/vtxprintf.c.
...
num = va_arg(args, unsigned int);
...
* Nils njaco...@hetnet.nl [110120 23:59]:
I investigated this some more and i think i found the problem.
The crosscompiler is working ok now and my coreboot rom has the same size as
the one from the automatic build system of coreboot.org exept for the SeaBios
payload mine is 46881 bytes and
Author: oxygene
Date: Fri Jan 21 08:04:05 2011
New Revision: 6282
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6282
Log:
There's another place where nvramtool can look for
the CMOS checksum specification.
When using nvramtool on files (instead of CMOS and runtime firmware)
it's the
Author: oxygene
Date: Fri Jan 21 08:18:20 2011
New Revision: 6283
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6283
Log:
Abstract CMOS accesses a bit more in preparation of using
files for CMOS data.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer
Author: oxygene
Date: Fri Jan 21 08:19:59 2011
New Revision: 6284
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6284
Log:
Add support for working on in-memory CMOS data (eg.
as loaded from a file).
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer
Author: oxygene
Date: Fri Jan 21 08:24:08 2011
New Revision: 6285
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6285
Log:
Add nvramtool -C option that takes a CBFS file as argument.
When using this option, nvramtool looks for a cmos_layout.bin
and cmos.default in the image and uses
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6282 to
the coreboot repository. This caused the following
changes:
Change Log:
There's another place where nvramtool can look for
the CMOS checksum specification.
When using
Author: oxygene
Date: Fri Jan 21 08:29:40 2011
New Revision: 6286
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6286
Log:
Add nvramtool -D option that allows taking cmos data from
a plain binary file. Overrides using cmos.default in CBFS
if both -C and -D are given.
Signed-off-by:
Author: stepan
Date: Fri Jan 21 08:46:32 2011
New Revision: 6287
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6287
Log:
push ts5300 rom size to 1MB. In fact the flash part on that
board is 2MB and the entry point is somewhere in the middle. quite weird setup
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6283 to
the coreboot repository. This caused the following
changes:
Change Log:
Abstract CMOS accesses a bit more in preparation of using
files for CMOS data.
Signed-off-by:
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