[coreboot] Trac reminder: list of new ticket(s)

Ticket Owner Status Description #170 ste...@coresystems.de new Need coreboot for ASUS P4PE_X/SE #169 ste...@coresystems.de new ASUS P4PE-X/SE. #168 ste...@coresystems.de new USBDEBUG might slow down coreboot

Re: [coreboot] [commit] r6293 - trunk/src/southbridge/amd/sb800

> Log: > Change fadt revision back to 3. > The AcpiPmaCntBlk have to be set. > Further research is needed to find out why. > > Signed-off-by: Zheng Bao > Acked-by: Zheng Bao > > Modified: >trunk/src/southbridge/amd/sb800/early_setup.c >trunk/src/southbridge/amd/sb800/fadt.c > > Modifi

[coreboot] Some questions about Intel 815EG GMCH

I wonder if you can introduce some active forums or mailing lists to discuss Intel chips in details technically except the Intel forums because they are virtually inactive and no question is answered i have tried it out before. I have questions about Intel 82815EG north bridge(it is connected to Pe

[coreboot] Patch for coreboot_table.c

This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue. Signed-off-by: Josef Kellermann ** IMPORTANT NOTICE / WICHTIGER HINWEIS This communicatio

Re: [coreboot] [PATCH] RS690 code booting RS740 with ECS A740GM-M

Peter Stuge writes: > Ivaylo Valkov wrote: >> Adds RS740 HT and internal graphics PCI ids. >> Adds support for RS740 in RS690 code (some of the fam10 code from RS780). >> Adds support for ECS A740GM-M. >> >> This definitely needs more patches and fine-tuning. >> Only tested on RS740. > > Please

[coreboot] [commit] r6294 - trunk/util/nvramtool

Author: ruik Date: Mon Jan 24 22:05:53 2011 New Revision: 6294 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6294 Log: Add CFLAGS when compiling resulting executable. It broke 64bit systems, because the rest uses -m32 now. Signed-off-by: Rudolf Marek Acked-by: Rudolf Marek Modifie

[coreboot] [commit] r6295 - trunk/src/arch/x86/boot

Author: stepan Date: Mon Jan 24 22:07:57 2011 New Revision: 6295 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6295 Log: This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue. Signed-off-by: Josef Kellermann Acked-by: Stefan Reinauer Modified: trunk/src/arc

Re: [coreboot] Patch for coreboot_table.c

* Joseph Kellermann [110124 18:33]: > This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue. > > Signed-off-by: Josef Kellermann Thanks for spotting this error. Your fix went into the repository as r6295. Best regards, Stefan Reinauer -- coreboot mailing list: coreboo

[coreboot] [commit] r6296 - trunk/util/nvramtool

Author: stepan Date: Mon Jan 24 22:27:22 2011 New Revision: 6296 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6296 Log: If the tool has 64bit issues, we need to find and fix them. No papering over them. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/u

Re: [coreboot] [PATCH] Use a tag for SeaBIOS stable checkouts.

* Peter Stuge [110124 00:35]: > > I neither want to check the changes I make to the config file in to > > the local repository > > Can we please not use perl for this? sed can do it just fine. Sure. Not all sed versions support in-place changes though, so the code will have to handle that. Just

Re: [coreboot] [PATCH] Use a tag for SeaBIOS stable checkouts.

On Tue, Jan 25, 2011 at 02:37:03AM +0100, Stefan Reinauer wrote: > * Peter Stuge [110124 00:35]: > > > +TAG-$(CONFIG_SEABIOS_MASTER)=origin/master > > > TAG-$(CONFIG_SEABIOS_STABLE)=rel-0.6.1.3 > > .. > > > checkout: > > > echo "Checking out SeaBIOS $(TAG-y)" > > > - test -d seabio

[coreboot] [commit] r6297 - trunk/src/southbridge/amd/sb800

Author: zbao Date: Tue Jan 25 07:06:58 2011 New Revision: 6297 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6297 Log: Set the SB800 SATA PHY correctly. Signed-off-by: Zheng Bao Acked-by: Zheng Bao Modified: trunk/src/southbridge/amd/sb800/sata.c Modified: trunk/src/southbridge

[coreboot] [PATCH]Make LPT ports configurable on various i945/ich7 boards

Hi, attached patch adds a new CMOS variable which triggers activation of the LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. There's probably a better place for the code to end up in, but this has to do for now. Signed-off-by: Patrick Georgi I