Hi
Thanks for the hint, I have seen that but it looks OK. I suspect my BootSwitch
(SATA/PATA channel select) might play some role... Not sure yet. I think
coreboot does not use combined mode at all. It sets all as IDE, and linux
switches the combined mode in quirks.c (quirk_amd_ide_mode)
Tha
On Sun, Jan 30, 2011 at 01:05:54PM -0700, Marc Jones wrote:
>
> I think that the locking can be added via the BSPs cache. All
> multicore should use CAR and it is a matter of adding it where it
> won't get stepped on by the normal use of CAR. For AMD fam10, the
> sysinfo setup would need to be fix
]Hi,
]
]I think SATA port 4 and 5 may have some issues on SB700 (not detecting drive
in
]linux and seabios)
]
]Dunno why. I did not have time to try AHCI mode yet. But I think we can drop
the
]wait for non BSY in coreboot beacuse the payload/linux should do that.
]
](the sata_drive_detect)
]
]
Hi,
I think SATA port 4 and 5 may have some issues on SB700 (not detecting drive in
linux and seabios)
Dunno why. I did not have time to try AHCI mode yet. But I think we can drop the
wait for non BSY in coreboot beacuse the payload/linux should do that.
(the sata_drive_detect)
Thanks,
Rud
On Sun, Jan 30, 2011 at 09:07:52PM +0100, Stefan Reinauer wrote:
> * xdrudis [110130 20:59]:
> > Yes, it'd be mostly unneeded, but anyway the patch I sent does not
> > disable it in ramstage. So it still causes sprintf to consume
> > the double of bytes maybe beyond its buffers (and produce
> >
On Fri, Jan 28, 2011 at 2:31 PM, Rudolf Marek wrote:
> Oh yes seems it is quite similar. I could not test this, I'm attaching the
> changes.
>
> Signed-off-by: Rudolf Marek
Acked-by: Marc Jones
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* xdrudis [110130 20:59]:
> Yes, it'd be mostly unneeded, but anyway the patch I sent does not
> disable it in ramstage. So it still causes sprintf to consume
> the double of bytes maybe beyond its buffers (and produce
> unreadable messages). The idea can work, the perl script may be
> usable,
On Sun, Jan 30, 2011 at 12:32 PM, Stefan Reinauer
wrote:
> * xdrudis [110130 15:46]:
>> On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
>> > is what I have. My board does not get to ramstage, so it might not
>> > work there. It works for my serial console but should work for net or
>>
>
On Sun, Jan 30, 2011 at 08:32:58PM +0100, Stefan Reinauer wrote:
> * xdrudis [110130 15:46]:
> > On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> > > is what I have. My board does not get to ramstage, so it might not
> > > work there. It works for my serial console but should work for n
#173: Build faiulre with gcc 4.4.3 because of src/pc80/mc146818rtc_early.c
unused
variable
--+--
Reporter: anonymous | Owner: stepan@…
Type: defect |Status: new
Priority: major | Mileston
* xdrudis [110130 15:46]:
> On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> > is what I have. My board does not get to ramstage, so it might not
> > work there. It works for my serial console but should work for net or
>
> Ok, now I see it. It won't work with sprintf in ramstage.
It
At Sun, 30 Jan 2011 06:59:39 +0100,
Stefan Reinauer wrote:
>
> * Dmitry Samoyloff [110129 22:07]:
> > I've tried to install Coreboot/SeaBIOS on my ASRock 939A785GMH/128M
> > motherboard [1], leaving it totally unbootable: no beeps, no VGA output :-(
>
> What's on serial console?
I can't check
At Sat, 29 Jan 2011 18:43:10 -0800 (PST),
Neo The User wrote:
>
> > > The motherboard's chip is Winbond W25Q80, 1024 KB.
> >
> > I also have ASUS M3A78-EM mobo with chip "Macronix
> > MX25L8005" (1024 KB,
> > SPI). Is it a good idea to hot swap these chips to try to
> > recover? Are they
> > int
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "oxygene" checked in revision 6320 to
the coreboot repository. This caused the following
changes:
Change Log:
Replace special rules for auxiliary files by cbfs-files-y entries
VGABIOS, Intel MBI and the bootsp
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "oxygene" checked in revision 6319 to
the coreboot repository. This caused the following
changes:
Change Log:
Inverse two arguments of cbfs-files-y and adapts its users (one of which
already used the new order
Am 29.01.2011 11:22, schrieb Peter Stuge:
>> +cbfs-files-$(CONFIG_VGA_BIOS) += pci$(call
>> strip_quotes,$(CONFIG_VGA_BIOS_ID)).rom
>> +pci$(CONFIG_VGA_BIOS_ID)-file := $(call
>> strip_quotes,$(CONFIG_VGA_BIOS_FILE))
>> +pci$(CONFIG_VGA_BIOS_ID)-type := optionrom
>
> These last two need .rom as
Author: oxygene
Date: Sun Jan 30 17:37:39 2011
New Revision: 6320
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6320
Log:
Replace special rules for auxiliary files by cbfs-files-y entries
VGABIOS, Intel MBI and the bootsplash image were added with special
build rules. These are replac
Author: oxygene
Date: Sun Jan 30 17:31:15 2011
New Revision: 6319
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6319
Log:
Inverse two arguments of cbfs-files-y and adapts its users (one of which
already used the new order)
This is in reponse to feedback that the original setup was to
Am 28.01.2011 22:02, schrieb Stefan Reinauer:
> Stuff like cmos.layout could arguably go into fallback/ or normal/.
> What's the right way to solve this with cbfs-files-y?
Use CONFIG_CBFS_PREFIX? Like:
cbfs-files-y += $(CONFIG_CBFS_PREFIX)/cmos.layout
$(CONFIG_CBFS_PREFIX)/cmos.layout-file := #and
Am 30.01.2011 16:04, schrieb xdrudis:
> Also wrong. Having several concurrent outputs with the same buffer id
> is not safe, demuxing could join the wrong half-characters.
>
> Filtering out some cores would be an option.
Or just use more bits for cores once the need arises. That will give you
up
On Sun, Jan 30, 2011 at 09:06:15AM +0100, Patrick Georgi wrote:
> Hi,
>
> given the large interest in using git by members of the community, I worked
> on
> an official read-only git mirror for general use.
> It has a website with code browser at
> http://code.coreboot.org/p/coreboot-git/
> an
On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> formats output. If someone has more than 16 cores does she really
> want to see ouput from all at a time? Redefining the weak function
> calc_id_buffer you can choose to have some of them mix into the same
> buffer or just filter out the
Am Sonntag, 30. Januar 2011, um 15:46:01 schrieb xdrudis:
> Forget it and sorry for the noise.
No need to be sorry, the idea is sound.
Patrick
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On Sat, Jan 29, 2011 at 11:09:05AM +0100, xdrudis wrote:
> is what I have. My board does not get to ramstage, so it might not
> work there. It works for my serial console but should work for net or
Ok, now I see it. It won't work with sprintf in ramstage.
I shouldn't have modified vtxprintf but
Hi Myles,
sorry to bother you directly, but Peter suggested to send the question
below to you directly, you may have an answer :)
Regards,
Sven.
Original Message
Subject: [coreboot] Question about new_resource()
Date: Thu, 27 Jan 2011 18:38:55 +0100
From: Sven Schnelle
Organi
Hi Danila,
I'd also like to say welcome, qa is definately something that
coreboot can benefit from.
Danila Sukharev wrote:
> As I see these docs are quite outdated... (about five years old)
Please do not assume outdated just because they are old. :) Some
details are outdated, e.g. the BIOS savi
Thanks to Patrick Georgi for finding this:
---
http://www.ohloh.net/p/coreboot/factoids/4229016
Very large, active development team
Over the past twelve months, 25 developers contributed new code to
coreboot.
This is one of the
Hi,
given the large interest in using git by members of the community, I worked on
an official read-only git mirror for general use.
It has a website with code browser at http://code.coreboot.org/p/coreboot-git/
and the repo URL is git://code.coreboot.org/coreboot-git.git
It's automatically upd
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