If I want to run gcc, ld , as from elf32-i386 toolchain, should i
change the file .xcompile in the root directory of Coreboot?
and change the following line:
CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none
to:
CC:=util/crossgcc/xgcc/i386-elf/bin/gcc -Wa,--divide
-fno-stack-protector
Am Montag, 7. Februar 2011, um 16:34:01 schrieb ali hagigat:
Will that be enough? (no need to change the system header files paths?
or other thing?)
Simply remove .xcompile - it's regenerated by the util/xcompile/xcompile tool
before next build, and it should find the cross compiler
Ticket
Owner
Status
Description
#174 ste...@coresystems.de new Unable to boot from qemu-kvm -- seems to be a cbfs problem
#170 ste...@coresystems.de new Need coreboot for ASUS P4PE_X/SE
#169 ste...@coresystems.de
Ivaylo Valkov writes:
Peter Stuge writes:
Ivaylo Valkov wrote:
Adds RS740 HT and internal graphics PCI ids.
Adds support for RS740 in RS690 code (some of the fam10 code from RS780).
Adds support for ECS A740GM-M.
This definitely needs more patches and fine-tuning.
Only tested on
Author: stuge
Date: Mon Feb 7 21:16:40 2011
New Revision: 6335
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6335
Log:
Reliably build arbitrary Kconfig-based revisions of SeaBIOS
Reliability is accomplished by checking out the desired SeaBIOS commitish
into a branch named 'coreboot'
Stefan Reinauer wrote:
slightly reworked to get rid of the perl calls (and to work with the
Unless there's a reason not to, please commit the revised version (plus
the one line change to src/arch/x86/Makefile.inc which I forgot to diff)
r6335
//Peter
--
coreboot mailing list:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stuge checked in revision 6335 to
the coreboot repository. This caused the following
changes:
Change Log:
Reliably build arbitrary Kconfig-based revisions of SeaBIOS
Reliability is accomplished by checking
Add NetBSD support to nvramtool.
Signed-off-by: jakll...@kollasch.net
Index: util/nvramtool/accessors/cmos-hw-unix.c
===
--- util/nvramtool/accessors/cmos-hw-unix.c (revision 6334)
+++ util/nvramtool/accessors/cmos-hw-unix.c
Hi,
I noticed that, other than initialization in almost every superio, the
'set' member of struct io_info doesn't seem to be referenced by the pnp
code. Worth the removing?
Jonathan Kollasch
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coreboot mailing list: coreboot@coreboot.org
On Sat, Feb 05, 2011 at 09:54:49PM +0200, Alex G. wrote:
Sorry about forgetting to attach the patch.
Alex
On 02/05/2011 09:50 PM, Alex G. wrote:
(See Patch)
This fixes the
ERROR: device PNP: 002e.207 index 98 has no mask.
that I have been getting on the W83627EHG.
Alex
Index: src/superio/winbond/w83627ehg/superio.c
===
--- src/superio/winbond/w83627ehg/superio.c (revision 6323)
+++ src/superio/winbond/w83627ehg/superio.c (working copy)
@@ -189,7 +189,7 @@
{ ops, W83627EHG_HWM, PNP_IO0
On Tue, Feb 08, 2011 at 03:48:44AM +0200, Alex G. wrote:
Maybe try something like:
{ ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }
Jonathan Kollasch
Thanks. Find attached the updated micropatch.
Alex
Fixes a problem with the W8327EHG driver, where the midi
Author: jakllsch
Date: Tue Feb 8 03:36:39 2011
New Revision: 6336
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6336
Log:
Place the W83627EHG MIDI base address mask in the correct position.
Corrects index 98 has no mask error at runtime.
Signed-off-by: Alexandru Gagniuc
On Tue, Feb 08, 2011 at 02:29:47AM +, Jonathan A. Kollasch wrote:
On Tue, Feb 08, 2011 at 03:48:44AM +0200, Alex G. wrote:
Maybe try something like:
{ ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }
Jonathan Kollasch
Thanks. Find attached the updated
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