Hello Keith,
Patrick nailed most of your questions on the head. Few of my comments
below.
On Thu, 17 Feb 2011 08:18:25 +0100, Georgi, Patrick
patrick.geo...@secunet.com wrote:
Am Mittwoch, den 16.02.2011, 23:52 -0500 schrieb Keith Hui:
For this single chip chipset, should I put everything into
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
Makefile | 77 ++---
1 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/Makefile b/Makefile
index 43be315..0754b15 100644
--- a/Makefile
+++ b/Makefile
@@ -183,38
Otherwise they exist in several object files, confusing the linker
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
payloads/libpayload/include/stdio.h |4 +---
payloads/libpayload/libc/printf.c |4
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
payloads/libpayload/bin/lpgcc |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
index 57015d5..80c2266 100755
--- a/payloads/libpayload/bin/lpgcc
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
Makefile | 19 +++
1 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/Makefile b/Makefile
index 0754b15..a233c13 100644
--- a/Makefile
+++ b/Makefile
@@ -202,6 +202,11 @@ $(call add-class,ramstage)
$(call
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
payloads/libpayload/include/pci/pci.h |1 +
payloads/libpayload/libpci/libpci.c |6 +-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/payloads/libpayload/include/pci/pci.h
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
Makefile | 223 ++---
Makefile.inc | 227 ++
2 files changed, 248 insertions(+), 202 deletions(-)
create mode 100644
The result of this patch series would be that the coreboot toplevel
Makefile contains only the build system logic and is usable for other
trees, such as libpayload (which I'd like to change so it builds libc,
libcurses, and libpci instead of/in addition to libpayload)
Patrick
--
Patrick Georgi
On Di, 2011-02-01 at 11:50 +0100, Patrick Georgi wrote:
The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.
ping?
--
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 -
Hi Peter,
Peter Stuge wrote:
In this image you can see the tester plugged into an Asus mainboard:
http://alpskari.asiantuntijat.org/~juhe/in-system-flasher/DSC08430.jpg
Sadly this URL does not work for me. :\
We have been suffering from a server crash, because of a power failure
in our
* Jørn Odberg jorn.odb...@gmail.com [110217 15:49]:
1) This is a Shuttle X27 , dual Intel Atom CPU 330.
This system is fairly similar to the Intel D945GCLF board that is
already supported by coreboot. You will have to adapt the SuperIO
settings in devicetree.cb and romstage.c to the ite/it8718f
* Keith Hui buu...@gmail.com [110217 05:52]:
Southbridge has...
bootblock.c for code required to make the whole ROM chip accessible
all ACPI stuff (will be a while before I can get to that)
There is some ACPI stuff in the northbridge, too. See Intel i945 and
sb i82801gx for an example.
one
* Patrick Georgi patrick.geo...@secunet.com [110217 09:55]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
index 0754b15..a233c13 100644
--- a/Makefile
+++ b/Makefile
-$(eval $(call create_cc_template,driver,S,-DASSEMBLY))
-$(eval $(call create_cc_template,smm,c))
-$(eval
* Patrick Georgi patrick.geo...@secunet.com [110217 08:44]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Can you support my motherboard???
Here is some links for the mb specs:
http://www.motherboard.cz/mb/soyo/sy-7vba133.htm
http://utils.hns.net.in/drivers/Motherboard/Soyo/SY-7vba133/m7vba13312.pdf
http://utils.hns.net.in/drivers/Motherboard/Soyo/SY-7vba133/
Here is the attachment link in case
* Georgi, Patrick patrick.geo...@secunet.com [110217 12:32]:
The result of this patch series would be that the coreboot toplevel
Makefile contains only the build system logic and is usable for other
trees, such as libpayload (which I'd like to change so it builds libc,
libcurses, and libpci
Carl-Daniel Hailfinger wrote:
If you tell me about the design constraints of your device, I can
probably come up with a flashrom driver which can reflash an 1 MByte ROM
in ~5 minutes or so. That will require some cooperation from your
device, but should be doable with ~270 bytes of RAM. Even
Author: stepan
Date: Thu Feb 17 21:47:49 2011
New Revision: 6371
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6371
Log:
Make Makefile.inc parser loop more generic
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Author: stepan
Date: Thu Feb 17 21:48:45 2011
New Revision: 6372
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6372
Log:
Handle compiler options for source classes more generically
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer
* Patrick Georgi patrick.geo...@secunet.com [110217 10:24]:
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
---
Makefile | 223 ++---
Makefile.inc | 227
++
2 files
José Neto wrote:
Can you support my motherboard???
No. You will have to do the development yourself, if you want it.
[Apollo PRO133x] [1106:0691]
+-01.0-[:01]00.0 Silicon Integrated Systems [SiS] 300/305
PCI/AGP VGA Display Adapter [1039:0300]
SiS is out of the
Am Freitag, den 18.02.2011, 03:55 +0100 schrieb Peter Stuge:
Patrick Georgi wrote:
The cmos.default code wasn't actually used so far, due to an oversight
when forward-porting this feature from an old branch.
- Extend walkcbfs' use by factoring out the stage handling into C code.
-
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