On Mon, Apr 11, 2011 at 8:48 PM, Stefan Reinauer
wrote:
> * Joesph Czerniak [110411 22:22]:
>> Hi,
>> I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It
>> has the following specs:
>>
>> Here are the quick specs (the more detailed specs are at the bottom):
>>
>> CPU: In
Tested on the RS785E platform with Linux
thanks
Acked-by: Kerry she
--
Best Regards
Kerry
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Marc Jones
Sent: Saturday, April 02, 2011 5:47 AM
To: Rudolf Marek
Cc: coreboot@coreboot.o
Author: kerry
Date: Tue Apr 12 03:12:46 2011
New Revision: 6488
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6488
Log:
Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This
fixes 4GB memory issues.
Signed-off-by: Marc Jones
Acked-by: Kerry she
Modified:
* Joesph Czerniak [110411 22:22]:
> Hi,
> I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It
> has the following specs:
>
> Here are the quick specs (the more detailed specs are at the bottom):
>
> CPU: Intel Atom N550 with an integrated northbridge
> Southbridge: Inte
Author: stepan
Date: Mon Apr 11 22:17:22 2011
New Revision: 6487
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6487
Log:
Unify use of post_code
Signed-off-by: Alexandru Gagniuc
A
Author: svens
Date: Mon Apr 11 21:43:50 2011
New Revision: 6486
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6486
Log:
PMH7: Add chip config
Signed-off-by: Sven Schnelle
Acked-by: Peter Stuge
Added:
trunk/src/ec/lenovo/pmh7/chip.h
Modified:
trunk/src/ec/lenovo/pmh7/pmh7.c
Author: svens
Date: Mon Apr 11 21:43:32 2011
New Revision: 6485
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6485
Log:
EC: Add Lenovo H8
Move the EC support code from the X60 mainboard to a generic
driver, as this EC is used in many thinkpads. Also move the
ACPI code to this director
I have updated the coreboot site with some further ARM info:
http://www.coreboot.org/ARM
OpenRD-Ultimate
http://www.globalscaletechnologies.com/t-openrdudetails.aspx
has a PCIe slot right on the back panel.
Maybe we should use this if this GSOC project gets approved.
-Bari
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coreboot mailing
Sven Schnelle wrote:
> Signed-off-by: Sven Schnelle
Acked-by: Peter Stuge
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coreboot mailing list: coreboot@coreboot.org
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Sven Schnelle wrote:
> Move the EC support code from the X60 mainboard to a generic
> driver, as this EC is used in many thinkpads. Also move the
> ACPI code to this directory for this reason.
>
> This patch also adds a chip config, so that the initial setting
> for basic register can be specified
Move the EC support code from the X60 mainboard to a generic
driver, as this EC is used in many thinkpads. Also move the
ACPI code to this directory for this reason.
This patch also adds a chip config, so that the initial setting
for basic register can be specified in devicetree.cb
Signed-off-by:
Signed-off-by: Sven Schnelle
---
src/ec/lenovo/pmh7/chip.h |9 +
src/ec/lenovo/pmh7/pmh7.c | 12
src/ec/lenovo/pmh7/pmh7.h |1 +
src/mainboard/lenovo/x60/devicetree.cb |1 +
src/mainboard/lenovo/x60/mainboard.c |7 ---
Stefan Reinauer writes:
>> diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu
>> new file mode 100644
>> index 000..d9275b5
>> --- /dev/null
>> +++ b/src/mainboard/emulation/qemu
> ...
>> +#include "southbridge/intel/i82801gx/nvs.h"
> ...
>> +printk(BIOS_INFO, "ACPI:
* Sven Schnelle [110410 21:05]:
> diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu
> new file mode 100644
> index 000..d9275b5
> --- /dev/null
> +++ b/src/mainboard/emulation/qemu
...
> +#include "southbridge/intel/i82801gx/nvs.h"
...
> + printk(BIOS_INFO, "ACPI: do
* Ruud Schramp (DT) [110411 16:00]:
> Hello guys,
>
> I am looking in the sourcecode of the dl145_g3 and noticed IPMI
> initialisation there (commented out). It refers a ipmi.c Does anyone
> have this code around?
I suggest you get in contact with the original authors.
Stefan
--
coreboot ma
On Sun, Apr 10, 2011 at 11:40 PM, Carl-Daniel Hailfinger
wrote:
> Hi Hamo,
>
> I wrote a CBFS design change proposal ~2 years ago which handled such issues
> just fine, but IIRC nobody had time to comment. I can try to dig it up
> again.
>
> Regards,
> Carl-Daniel
Can you send your change to me?
Hello guys,
I am looking in the sourcecode of the dl145_g3 and noticed IPMI
initialisation there (commented out). It refers a ipmi.c Does anyone
have this code around?
Best regards,
Ruud
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Ticket
Owner
Status
Description
#176 ste...@coresystems.de new inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29e0
#174 ste...@coresystems.de new Unable to boot from qemu-kvm -- seems to be a cbfs problem
#170 ste...@core
As requested:
root@Microknoppix:~# isadump -y -k 0x5A 0x2e 0x2f 0
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 02 c0 00 05 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00
On Mon, Apr 11, 2011 at 08:52:56AM +0200, Ruud Schramp (DT) wrote:
> Updated
>
> Signed-off-by: Ruud Schramp
Thanks, r6484 with some minor cosmetic changes.
Can you post a full dump of all LDNs (0-15) using isadump? Maybe you can
guess a few more LDN names at least, judging from the register
c
Author: uwe
Date: Mon Apr 11 09:46:27 2011
New Revision: 6484
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6484
Log:
Add detection/dump support for ServerEngines SE-SM 4210-P01.
Note that the registers and their defaults are mostly based on educated
guessing, due to the lack of datas
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