Thank you,
This evening I will attempt to verify the 8 pin device noted, below the lower
right corner of the cardbus and below the TI PCI7412 Chip lower left. I will
reply to all with the BIOS chip info details later on.
John
-Original Message-
From: Idwer Vollering
Say hi to the four GSoC students working with coreboot this summer.
Hamo, Leandro, Stefan, and Tadas. You should be seeing more from them
on the mail list and in IRC. Please make them welcome. They will also
be keeping us all up to date on their progress on
http://blogs.coreboot.org.
Marc
--
We found this with some testing at BTDC. This patch sets max freq
defaults for ddr2 and ddr3for fam10. It may be overridden by a
developer setting it in romstage.c.
Signed-off-by: Marc Jones marcj...@gmail.com
--
http://se-eng.com
This patch sets max freq defaults for ddr2 and ddr3. It may be
Am 26.04.2011 15:59, schrieb Marc Jones:
We found this with some testing at BTDC. This patch sets max freq
defaults for ddr2 and ddr3for fam10. It may be overridden by a
developer setting it in romstage.c.
Please find a better place for that. This way of doing things relies on
us including code
Marc Jones wrote:
]We found this with some testing at BTDC. This patch sets max freq
]defaults for ddr2 and ddr3for fam10. It may be overridden by a
]developer setting it in romstage.c.
]
]Signed-off-by: Marc Jones marcj...@gmail.com
Acked-by: Scott Duplichan [sc...@notabs.org]
--
coreboot
On 26.04.2011, at 07:40, Den nis dnns...@gmail.com wrote:
Hi,
Im trying to port the iwave RainbowG6 coreboot code to a platform with the
same CPU (Intel Atom Z530) and chipset (Intel US15W), 1GB RAM (2 ranks, 1024
Mbits device density, x16 device width) and a winbond WPCN381U superio
* Patrick Georgi patr...@georgi-clan.de [110426 16:41]:
Am 26.04.2011 15:59, schrieb Marc Jones:
We found this with some testing at BTDC. This patch sets max freq
defaults for ddr2 and ddr3for fam10. It may be overridden by a
developer setting it in romstage.c.
Please find a better place
Am 26.04.2011 21:14, schrieb Stefan Reinauer:
Is that something we could reasonably put into devicetree.cb, given we'd
do an extra parse step to produce something that can be used by
romstage?
As an option (register) attached to the northbridge? I think that
could work, too.
Just that we don't
On 04/26/2011 10:16 AM, Marc Jones wrote:
Say hi to the four GSoC students working with coreboot this summer.
Hamo, Leandro, Stefan, and Tadas. You should be seeing more from them
on the mail list and in IRC. Please make them welcome. They will also
be keeping us all up to date on their progress
Stefan Reinauer wrote:
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.
This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.
Signed-off-by: Stefan Reinauer
Joseph Smith wrote:
Say hi to the four GSoC students working with coreboot this summer.
Hello Hamo, Leandro, Stefan, and Tadas! Welcome to coreboot, glad
to have you :-)
Yes, good fun! I'm looking forward to the projects!
//Peter
--
coreboot mailing list: coreboot@coreboot.org
Author: stepan
Date: Wed Apr 27 01:47:04 2011
New Revision: 6544
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6544
Log:
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.
This newer version reflects the recent changes to further simplify the console
On Tue, Apr 26, 2011 at 8:41 AM, Patrick Georgi patr...@georgi-clan.de wrote:
Am 26.04.2011 15:59, schrieb Marc Jones:
We found this with some testing at BTDC. This patch sets max freq
defaults for ddr2 and ddr3for fam10. It may be overridden by a
developer setting it in romstage.c.
Please
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