On 6/4/11 10:47 AM, Sven Schnelle wrote:
could be used for various things if the OS doesn't provide
ACPI support, or has ACPI disabled. The current patch only
uses this to enable operation of the backlight hotkeys.
As the Thinkpad EC doesn't support EC_QUERY on ports 0x1600/0x1604
and there are
On 6/4/11 10:47 AM, Sven Schnelle wrote:
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Signed-off-by: Sven Schnelle
Acked-by: Stefan Reinauer
---
src/include/cpu/x86/smm.h
On 6/4/11 3:22 PM, dove - railing wrote:
I am not a techie.
Would it be correct to say that fonts at the Bios level are decided by
the Video card / VGA firmware?
The VGA BIOS loads the initial font.
Is there an opensource utility for them?
I found this, it's not open source though:
http:/
I am not a techie.
Would it be correct to say that fonts at the Bios level are decided by the
Video card / VGA firmware? Is there an opensource utility for them?
Regards,
Meeku
--
coreboot mailing list: coreboot@coreboot.org
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could be used for various things if the OS doesn't provide
ACPI support, or has ACPI disabled. The current patch only
uses this to enable operation of the backlight hotkeys.
As the Thinkpad EC doesn't support EC_QUERY on ports 0x1600/0x1604
and there are no event queue registers in the EC register
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.
Signed-off-by: Sven Schnelle
---
src/include/cpu/x86/smm.h |2 +-
src/southbridge/intel/i82801gx/smihandler.c |
Stefan Reinauer wrote:
> > previous patches committed to svn, which were blindly applied to
> > asrock/e350m1
>
> Blindly copy'n'pasting code is not always the answer.
Of course not. The situation here is that we worked toward zero
differences between a nicely formatted patch set, and the single
Author: stepan
Date: Sat Jun 4 18:30:27 2011
New Revision: 6637
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6637
Log:
WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/mainboard/advansus/a785
* Peter Stuge [110604 18:19]:
> Stefan Reinauer wrote:
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:45:12
> > > 2011(r6627)
> > > @@ -50,6 +50,13 @@
> > >// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot
> > > time
> > >__writemsr (0xc0
* Peter Stuge [110604 18:16]:
> Stefan Reinauer wrote:
> > > +++ trunk/src/mainboard/asrock/e350m1/romstage.c Sat Jun 4 17:44:31
> > > 2011(r6625)
> ..
> > > +__outdword (0xcf8, 0x8000a3a0);
> >
> > what's the reason to not use pci_read_config32() here?
>
>
> > > +++ trunk/src/ma
Stefan Reinauer wrote:
> > +++ trunk/src/mainboard/asrock/e350m1/romstage.cSat Jun 4 17:45:12
> > 2011(r6627)
> > @@ -50,6 +50,13 @@
> >// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
> >__writemsr (0xc0010062, 0);
> >
> > + // early enable of Pref
* repository service [110604 17:47]:
> Author: stuge
> Date: Sat Jun 4 17:47:05 2011
> New Revision: 6633
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633
>
> Log:
> Port persimmon r6591 to e350m1: ROM cache early
>
> Enable rom cache early to reduce boot time.
>
> Signed-off-b
Stefan Reinauer wrote:
> > +++ trunk/src/mainboard/asrock/e350m1/romstage.cSat Jun 4 17:44:31
> > 2011(r6625)
..
> > +__outdword (0xcf8, 0x8000a3a0);
>
> what's the reason to not use pci_read_config32() here?
> > +++ trunk/src/mainboard/asrock/e350m1/romstage.cSat Jun 4 17
* repository service [110604 17:45]:
> Author: stuge
> Date: Sat Jun 4 17:45:12 2011
> New Revision: 6627
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
>
> Log:
> Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
>
> Enable SPI cacheline prefetch early to reduce bo
* repository service [110604 17:44]:
> Author: stuge
> Date: Sat Jun 4 17:44:54 2011
> New Revision: 6626
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626
>
> Log:
> Port persimmon r6583 to e350m1: pstate 0 early
>
> Switch processor cores to pstate 0 early to reduce boot time.
* repository service [110604 17:44]:
> Author: stuge
> Date: Sat Jun 4 17:44:31 2011
> New Revision: 6625
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
>
> Modified: trunk/src/mainboard/asrock/e350m1/romstage.c
>
mbusch...@lucidmachines.com wrote:
> From: Scott Duplichan
>
> 1) Set I/O APIC ID according to BKDG recommendation
> 2) Correct I/O APIC ID reported by mptable
>
> Signed-off-by: Marshall Buschman
All are either
Acked-by: Peter Stuge
or
Acked-by: Marshall Buschman
per IRC. Committed as r
Author: stuge
Date: Sat Jun 4 17:48:14 2011
New Revision: 6636
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6636
Log:
Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge
Acked-by: Marshall Buschman
Modified:
trunk/src/mainboard/asrock/e350m1/get_bus_con
Author: stuge
Date: Sat Jun 4 17:47:56 2011
New Revision: 6635
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6635
Log:
Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge
Acked-by: Marshall Buschman
Modified:
trunk/src/mainboard/asrock/e350m
Author: stuge
Date: Sat Jun 4 17:47:30 2011
New Revision: 6634
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6634
Log:
Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge
Acked-by: Marshall Buschman
Modified:
trunk/src/mainboard/asrock/e350m
Author: stuge
Date: Sat Jun 4 17:47:05 2011
New Revision: 6633
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6633
Log:
Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.
Signed-off-by: Marshall Buschman
Acked-by: Peter Stuge
Modified:
t
Author: stuge
Date: Sat Jun 4 17:46:50 2011
New Revision: 6632
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6632
Log:
Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.
Signed-off-by: Mar
Author: stuge
Date: Sat Jun 4 17:46:32 2011
New Revision: 6631
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6631
Log:
Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.
Signed-off-by: Marshall Buschman
Acked-by: Pe
Author: stuge
Date: Sat Jun 4 17:46:13 2011
New Revision: 6630
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6630
Log:
Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.
Signed-off-by: Marshall Buschman
Ac
Author: stuge
Date: Sat Jun 4 17:45:46 2011
New Revision: 6629
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6629
Log:
Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Marshall Buschman
Acked-by: P
Author: stuge
Date: Sat Jun 4 17:45:29 2011
New Revision: 6628
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6628
Log:
Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.
Signed-off-by: Marshall Buschman
Acked-by
Author: stuge
Date: Sat Jun 4 17:45:12 2011
New Revision: 6627
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6627
Log:
Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Marshall Buschman
Acked-by: Pe
Author: stuge
Date: Sat Jun 4 17:44:54 2011
New Revision: 6626
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6626
Log:
Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Marshall Buschman
Acked-by: Peter Stuge
Author: stuge
Date: Sat Jun 4 17:44:31 2011
New Revision: 6625
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6625
Log:
Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.
Signed-off-by: Marshall Buschman
Acked-by: Peter
Author: stuge
Date: Sat Jun 4 17:44:14 2011
New Revision: 6624
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6624
Log:
Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.
Signed-off-by: Peter Stuge
Acked-by: Peter Stug
Author: stuge
Date: Sat Jun 4 17:43:56 2011
New Revision: 6623
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6623
Log:
Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Marshall Buschman
Acked-by: Peter Stuge
Modified:
Author: stuge
Date: Sat Jun 4 17:43:38 2011
New Revision: 6622
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6622
Log:
Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dff
Author: stuge
Date: Sat Jun 4 17:43:15 2011
New Revision: 6621
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6621
Log:
Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Marshall B
Author: stuge
Date: Sat Jun 4 17:40:12 2011
New Revision: 6620
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6620
Log:
vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the previou
Add ACPI automatic PIC/APIC interrupt routing logic for ck804.
Signed-off-by: Jonathan Kollasch
Index: src/southbridge/nvidia/ck804/acpi/ck804.asl
===
--- src/southbridge/nvidia/ck804/acpi/ck804.asl (revision 0)
+++ src/southbridge/n
On Fri, Jun 03, 2011 at 12:44:22PM -0600, Marc Jones wrote:
> Revert changes to set the sb800 to AHCI mode. Seabios doesn't have
> this support included yet, which causes the generic Persimmon and
> other CIMx sb800 platforms to not boot.
>
> Signed-off-by: Marc Jones
Acked-by: Jonathan Kollasch
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