[coreboot] [PATCH] asrock e350m1: configure sb800 gpp ports to support onboard pcie nic

The attached patch allows the asrock e350m1 onboard nic to work. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component

[coreboot] New patch to review: 69f0b38 Add SMSC SCH3114 superio register descriptions to superiotool.

Mark Norman (mpnor...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/43 -gerrit commit 69f0b386a0ffc9a5d78818626e7ebf500a1db012 Author: Mark Norman Date: Sat Jun 18 10:24:36 2011 +0930 Add SMSC SCH3114 superio register descriptions to

Re: [coreboot] caching in SMI handler

Hi Sven, On Fri, Jun 17, 2011 at 6:51 AM, Sven Schnelle wrote: > Hi List, > > i've encountered an interesting problem on my Thinkpad T60: > > whenever i've docked/undocked the thinkpad from the docking station, > i had to do that twice to get the action actually to happen. > > First i thought tha

[coreboot] New patch to review: c40cd03 T60: set dock LED's in mainboard.c

Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/42 -gerrit commit c40cd035a5cc85e33a20016c7347a1fa392fcc89 Author: Sven Schnelle Date: Fri Jun 17 21:26:28 2011 +0200 T60: set dock LED's in mainboard.c

Re: [coreboot] Questions about CBFS

Am 17.06.2011 16:36, schrieb Hamo: > You mean that we use MSB as default now? I think there's an exception for one field (entry point?), but other than that, yes. > A new question: > Why we use a binary file to create the rom but using an ELF to add a > stage to this rom? Mostly historical reasons

[coreboot] New patch to review: 0f56ebb SMM: flush caches after disabling caching

Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/39 -gerrit commit 0f56ebbc8996cf760b6a2486f730f47664780568 Author: Sven Schnelle Date: Fri Jun 17 20:47:08 2011 +0200 SMM: flush caches after disabling caching

Re: [coreboot] Questions about CBFS

On Fri, Jun 17, 2011 at 2:29 PM, Georgi, Patrick wrote: > Am Donnerstag, den 16.06.2011, 21:50 +0800 schrieb Hamo: > We thought it's a good idea to mandate _some_ default, otherwise we'd > risk having incompatible image formats created by the same tool. > You mean that we use MSB as default now? >

[coreboot] caching in SMI handler

Hi List, i've encountered an interesting problem on my Thinkpad T60: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how docking

Re: [coreboot] coreboot support: difference between ASRock E350M1 and ASRock E350M1/USB3

Marshall Buschman wrote: ]I own both boards - both do work, BUT there are still bugs: ]USB3 and built-in NIC do not work on either by default. ]Memory is only reported as roughly 512mb at this point. ] ]You're welcome to help. :) Hello Marshall, Thanks for reporting these problems. Incorrect mem