the following patch was just integrated into master:
commit 5f1cfd8ee9d400f20a5aa30eb50b9afb5e2694db
Author: Kevin O'Connor
Date: Sat Jul 9 20:22:21 2011 -0400
Do full flush on uart8250 only at end of printk.
The previous code does a full flush of the uart after every character.
Hi Scott. Thanks a lot for testing!
On 2011.07.12 02:38, Scott Duplichan wrote:
I tried the
sample on ASRock E350M1 and it did not work. One reason is needed LPC
clock initialization (http://permalink.gmane.org/gmane.linux.bios/67229).
OK.
I'm obviously a bit nervous about changing a clock fr
On 2011.07.12 07:05, Patrick Georgi wrote:
"Panic Room" features won't be too useful for flash recovery.
With partial flash updates and the fallback/normal bootblock it should
be possible to build a recoverable update mechanism.
I'd tend to agree that, if you already have coreboot working, fall
Hi Tadas,
On 2011.07.12 02:42, Tadas Slotkus wrote:
currently my plan is to run flashrom out of cache (in romstage),
transfer rom image over console (serial, maybe later ne2k) in small
chunks like ~256 bytes so that cache_as_ram.inc would require less
changes.
That sounds good (and quite a lot
I only started looking into coreboot yesterday, so forgive the
incoming naivety.
Can anyone point me in the direction of how to set up coreboot + seabios so
that it actually uses the VGA? I've got the system up and running and
talking to me over the OS's services fine, so all is working except for
On 12 July 2011 15:31, Benjamin Henrion wrote:
> On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster
> wrote:
> >
> > I only started looking into coreboot yesterday, so forgive the
> incoming naivety.
> > Can anyone point me in the direction of how to set up coreboot + seabios
> so that it actually
On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster wrote:
>
> I only started looking into coreboot yesterday, so forgive the
> incoming naivety.
> Can anyone point me in the direction of how to set up coreboot + seabios so
> that it actually uses the VGA? I've got the system up and running and talk
On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote:
>
> - my objective was to install coreboot on my new board MA785GMT-UDH2. I had
> bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big
> problems because:
[...]
> coreboot and give it a run, but I will do th
On Tue, Jul 12, 2011 at 8:38 AM, Andrew Bolster wrote:
> On 12 July 2011 15:31, Benjamin Henrion wrote:
>>
>> On Tue, Jul 12, 2011 at 3:18 PM, Andrew Bolster
>> wrote:
>> >
>> > I only started looking into coreboot yesterday, so forgive the
>> > incoming naivety.
>> > Can anyone point me in the
On Tue, Jul 12, 2011 at 10:18 AM, xdrudis wrote:
> On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote:
>>
>> - my objective was to install coreboot on my new board MA785GMT-UDH2. I had
>> bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big
>> problems becau
On 2011.07.12 07:15, Andrew Goodbody wrote:
Instead of attempting (and failing) to achieve universal support
I'll start with the aside, that if "failing" means instantly supporting
more than 90% of Intel based motherboards produced in the last 10 years
(if you have an ICH# or a 440BX controll
Andrew Bolster wrote:
> Can anyone point me in the direction of how to set up coreboot +
> seabios so that it actually uses the VGA?
Are you sure there actually is VGA? For the Geode SC series it was
neccessary to have a VSM that would emulate a fair bit of the legacy
VGA. I think LX has some hard
Andrew Bolster wrote:
> Can anyone point me in the direction of how to set up coreboot +
> seabios so that it actually uses the VGA?
I am struggling with the same problem for some time now.
Extracting the original VGA as Peter suggests won't work because the LX
VSA we use is stripped down and does
the following patch was just integrated into master:
commit 77439f041fc6348cdaaa682d5cbe8c41f3f96241
Author: Rudolf Marek
Date: Sat Jul 2 16:36:17 2011 +0200
Make AMD SMM SMP aware
Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE
define,
later all 0xa
the following patch was just integrated into master:
commit 835a320916cd7a5032750b1fe1ca0df37a33f198
Author: Rudolf Marek
Date: Sat Jul 2 16:41:38 2011 +0200
Enable SMI on M2V-MX SE
Finally the SMI routines are in good shape on AMD, lets enable this and
later
implement ACPI on
> -Original Message-
> From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
> On Behalf Of xdrudis
> Sent: Wednesday, July 13, 2011 12:18 AM
> To: Florentin Demetrescu
> Cc: coreboot@coreboot.org
> Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011
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