[coreboot] New patch to review: bcdf12b Update AMD family10 northbridge wrapper, supermicro/h8qgi mainboard

2011-07-26 Thread shekai...@gmail.com
Kerry She (shekai...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/121 -gerrit commit bcdf12b47bc8c01bf3b4f18df4bc343fcd517a82 Author: Kerry She Date: Wed Jul 27 14:13:35 2011 +0800 Update AMD family10 northbridge wrapper, supermicro

Re: [coreboot] Questions about how to record hardware information on ARM

2011-07-26 Thread Marc Jones
On Tue, Jul 26, 2011 at 5:03 PM, Hamo wrote: >> Are you thinking of extending the resource allocator? How does uboot >> do this? What would your device tree look like? > the resource allocator is based on PCI bus. We need a device's bus > number and device number to allocate resources to it. But o

Re: [coreboot] Questions about how to record hardware information on ARM

2011-07-26 Thread Hamo
> Devices that can not be probed have to be put in the static device > tree. Coreboot has support for a number of those, SuperIOs for example. > current static device tree is based on PCI bus. every device should under a PCI domain and have its own PCI bus number and device number. This is the prob

Re: [coreboot] Questions about how to record hardware information on ARM

2011-07-26 Thread Hamo
> Are you thinking of extending the resource allocator? How does uboot > do this? What would your device tree look like? the resource allocator is based on PCI bus. We need a device's bus number and device number to allocate resources to it. But on ARM, no devices are connected to a PCI bus. So the

Re: [coreboot] a couple gerrit things

2011-07-26 Thread Patrick Georgi
Am Samstag, den 16.07.2011, 09:23 -0600 schrieb Marc Jones: > Can the gerrit merge emails include the reviewers/commiter ID? The mails to the list? Can do, but that requires some JSON parsing that need to hack up. > Gerrit (or the hook?) prevents pushing a new patch without the signoff > of the p

[coreboot] Patch set updated: dbbd75f split CBFS support into shared core and extended functions

2011-07-26 Thread patr...@georgi-clan.de
Patrick Georgi (patr...@georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/114 -gerrit commit dbbd75f386d59eafd7d07a2e7df21527ce156898 Author: Patrick Georgi Date: Thu Jul 21 15:11:40 2011 +0200 split CBFS support into shared core an

[coreboot] Patch set updated: 70d49a6 libpayload: Add liblzma, libcbfs

2011-07-26 Thread patr...@georgi-clan.de
Patrick Georgi (patr...@georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/115 -gerrit commit 70d49a6ab5036edd254261d4b3045590eadb7cbe Author: Patrick Georgi Date: Thu Jul 21 15:43:14 2011 +0200 libpayload: Add liblzma, libcbfs

[coreboot] Patch merged into master: 7ebb9bf crossgcc: update w32api

2011-07-26 Thread gerrit
the following patch was just integrated into master: commit 7ebb9bfe774bdefd57b9f8decf2b7cfd9a130f08 Author: Patrick Georgi Date: Sat Jul 23 23:29:44 2011 +0200 crossgcc: update w32api crossgcc also needs lzma support as w32api is distributed in .tar.lzma Change-Id: Ia1938

[coreboot] Patch set updated: 7ebb9bf crossgcc: update w32api

2011-07-26 Thread patr...@georgi-clan.de
Patrick Georgi (patr...@georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/120 -gerrit commit 7ebb9bfe774bdefd57b9f8decf2b7cfd9a130f08 Author: Patrick Georgi Date: Sat Jul 23 23:29:44 2011 +0200 crossgcc: update w32api cross

[coreboot] [RFC] UBRX v0.2

2011-07-26 Thread Pete Batard
On 2011.07.18 04:14, Scott Duplichan wrote: I have an AMD SB900 board with Nuvoton NCT6776F. To make the serial port work on this board, two pieces of non-generic code are needed. As promised, I have now updated UBRX to support SB900 boards and NCT6776F SIOs. As for the SB800, the SB900 init

Re: [coreboot] Questions about how to record hardware information on ARM

2011-07-26 Thread Stefan Reinauer
* Hamo [110726 11:05]: > Hi lists, > As I have moved forward to writing the ramstage, much more problems came out. > PCI devices are just extra devices that can be used but not key > devices like those on X86. Most devices on ARM are connected through > AHBA bus and can be configured by reading an

Re: [coreboot] Questions about how to record hardware information on ARM

2011-07-26 Thread Marc Jones
Hamo, On Tue, Jul 26, 2011 at 3:05 AM, Hamo wrote: > Hi lists, > As I have moved forward to writing the ramstage, much more problems came out. > PCI devices are just extra devices that can be used but not key > devices like those on X86. Most devices on ARM are connected through > AHBA bus and c

[coreboot] Patch merged into master: 036c126 buildgcc: Break if parts of the toolchain are missing

2011-07-26 Thread gerrit
the following patch was just integrated into master: commit 036c126975c8c2edb198759d06ee1694c26068aa Author: Patrick Georgi Date: Sun Jul 17 11:36:10 2011 +0200 buildgcc: Break if parts of the toolchain are missing We test for the presence of a couple of tools and even print an err

[coreboot] Questions about how to record hardware information on ARM

2011-07-26 Thread Hamo
Hi lists, As I have moved forward to writing the ramstage, much more problems came out. PCI devices are just extra devices that can be used but not key devices like those on X86. Most devices on ARM are connected through AHBA bus and can be configured by reading and writing data from and into the c