Vikram Narayanan (vikram...@gmail.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/576
-gerrit
commit 07a809248b817de1f1476cf84d4b89f8e98e43eb
Author: Vikram Narayanan vikram...@gmail.com
Date: Tue Jan 24 19:17:47 2012 +0530
pci_ops_conf:
Vikram Narayanan (vikram...@gmail.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/577
-gerrit
commit 4730e47a8b3553bc55b1a9c2b7863e3b6fd9ec31
Author: Vikram Narayanan vikram...@gmail.com
Date: Tue Jan 24 20:18:56 2012 +0530
pci_ops_mmconf:
Vikram Narayanan (vikram...@gmail.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/578
-gerrit
commit 4d00fc2cc948df00447b1140dbcb8cccaa816cac
Author: Vikram Narayanan vikram...@gmail.com
Date: Tue Jan 24 20:22:20 2012 +0530
pci_ops_mmconf:
Hello all,
Creator of the ADLO fame (http://www.coreboot.org/ADLO) is back from
sabbatical and is looking for a job.
Preferably something linuxbios^w coreboot related but I am open for other
options.
Preferred country to live at is Norway.
Sincerely,
Adam Sulmicki
--
coreboot mailing list:
On Monday 23 January 2012 22:35:22 Scott Duplichan wrote:
Prakash Punnoor wrote:
]So, I cannot make coreboot boot. On cold start it seems to hang in
]
]src/southbridge/amd/sb700/reset.c
]
]in soft_reset. set_bios_reset seems sucessful, but I get no post code after
]outb(0x06, 0x0cf9).
On Tue, Jan 24, 2012 at 5:38 AM, Wolfgang Kamp - datakamp
wmk...@datakamp.de wrote:
Hi Marc,
DIMM address and i2c address are ok.
Please look at the log. I think the SB800 is unaccessable.
Regards
Wolfgang
The sb800 is accessible, it is fetching rom and initializing devices
that it
the following patch was just integrated into master:
commit 07a809248b817de1f1476cf84d4b89f8e98e43eb
Author: Vikram Narayanan vikram...@gmail.com
Date: Tue Jan 24 19:17:47 2012 +0530
pci_ops_conf: Indentation fixes
Indentation fixes in src/arch/x86/lib/pci_ops_conf{1,2}.c
the following patch was just integrated into master:
commit f878bc41e0e6c46eab928c7bcb1330e22a4f5237
Author: Marc Jones marcj...@gmail.com
Date: Fri Jan 13 14:39:48 2012 -0700
AMD Mahogany Fam10 ACPI table fixes.
Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2
the following patch was just integrated into master:
commit c52e62de11ca8c0bc92677794fbfe2f0fb331ea8
Author: Kerry Sheh shekai...@gmail.com
Date: Fri Jan 20 13:58:53 2012 +0800
RD890: pci_ids update
RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX
chipsets,
Prakash Punnoor wrote:
]BTW, could you explain what happens after soft_reset? Will coreboot run
]again from start?
Yes, the CF9 soft reset starts execution at the reset vector
same as a cold boot.
] At least the following die(...) statement (romstage.c
]cache_as_ram_main) suggests that
the following patch was just integrated into master:
commit d9da3f007263804da7c941ee5631bffccd7fa76a
Author: Dave Frodin dave.fro...@se-eng.com
Date: Thu Jan 19 14:28:32 2012 -0700
Mahogany Fam10 MPtable fix
Make changes MPtable to match ACPI tables.
Change-Id:
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