[coreboot] New patch to review for coreboot: f548d59 Intel cpus: use CPU_PHYSMASK_HI define in CAR

2012-02-15 Thread kyosti.mal...@gmail.com
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/638 -gerrit commit f548d593f020bd56c1bb7fa75ea8d6cb11cb0428 Author: Kyösti Mälkki kyosti.mal...@gmail.com Date: Wed Feb 15 15:55:57 2012 +0200 Intel cpus: use

[coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)?

2012-02-15 Thread Idwer Vollering
Or: how to start a multicore (hyperthreading) processor as if it were a singlecore (non-hyperthreading) processor. Would it be necessary to configure APIC/IPI in serialice' mainboard specific code? See these message [1] [2] [3]. This is the output from two processors with hyperthreading disabled

[coreboot] Patch merged into coreboot/master: e8a4832 Intel model_106cx: Use symbolic names for MTRR bits

2012-02-15 Thread gerrit
the following patch was just integrated into master: commit e8a4832907c4ff5d126c32acde22a00ad35b6395 Author: Kyösti Mälkki kyosti.mal...@gmail.com Date: Wed Feb 15 15:55:03 2012 +0200 Intel model_106cx: Use symbolic names for MTRR bits Change-Id:

Re: [coreboot] [SerialICE] Which MSR disables hyperthreading (all non-BSP/AP cores)?

2012-02-15 Thread Stefan Reinauer
* Idwer Vollering vid...@gmail.com [120215 17:33]: Or: how to start a multicore (hyperthreading) processor as if it were a singlecore (non-hyperthreading) processor. Would it be necessary to configure APIC/IPI in serialice' mainboard specific code? You probably need something like:

Re: [coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)?

2012-02-15 Thread Kyösti Mälkki
On Wed, 2012-02-15 at 17:33 +0100, Idwer Vollering wrote: Or: how to start a multicore (hyperthreading) processor as if it were a singlecore (non-hyperthreading) processor. To my knowledge, there is no such MSR for P4 Hyper-Threaded CPUs using the NetBurst Architecture. So SerialICE may need

[coreboot] Patch merged into coreboot/master: f548d59 Intel cpus: use CPU_PHYSMASK_HI define in CAR

2012-02-15 Thread gerrit
the following patch was just integrated into master: commit f548d593f020bd56c1bb7fa75ea8d6cb11cb0428 Author: Kyösti Mälkki kyosti.mal...@gmail.com Date: Wed Feb 15 15:55:57 2012 +0200 Intel cpus: use CPU_PHYSMASK_HI define in CAR Unifies models 6ex, 6fx and 106cx.

Re: [coreboot] flash-chip (and compatibles)

2012-02-15 Thread Oliver Schinagl
I was pointed to this one: A25L032-F http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085 (There's also a Q version, which I don't think is what I'd want).

Re: [coreboot] flash-chip (and compatibles)

2012-02-15 Thread Peter Stuge
Oliver Schinagl wrote: I was pointed to this one: A25L032-F http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085 (There's also a Q version, which I don't think is what I'd want). Correct. Q is a WSON package which does not fit at all. Make sure you buy farnell nr.