Paul Menzel (paulepan...@users.sourceforge.net) just uploaded a new patch set
to gerrit, which you can find at http://review.coreboot.org/2586
-gerrit
commit b8b58e0a5e8ccc8b808c13d2c0f91ccecd209ab3
Author: Paul Menzel paulepan...@users.sourceforge.net
Date: Mon Mar 4 18:57:28 2013 +0100
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2585
-gerrit
commit 7f9f5f80c9dc5de2ebfdfa9927d19f1454b47785
Author: Ronald G. Minnich rminn...@gmail.com
Date: Mon Mar 4 16:39:35 2013 -0800
google/snow: Change
Hi Martin (and all),
I wrote:
You dereference dev in line 132, so if it's really 0,
will you then ever reach this check?? (I don't know if
in romstage *NULL is caught.)
You wrote:
yes, if it's 0, we still reach the code. I've changed it
to not dereference it before checking it though.
Per
Ronald G. Minnich (rminn...@gmail.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2587
-gerrit
commit 840574bcf408d9b66904600c99af280fb4b3b9df
Author: Ronald G. Minnich rminn...@gmail.com
Date: Wed Mar 6 08:50:50 2013 -0800
Google/Snow:
Aladyshev Konstantin (ko...@list.ru) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2588
-gerrit
commit efd2e87412cb0808051e4c45c654da77d8b685c0
Author: Konstantin Aladyshev aladys...@nicevt.ru
Date: Wed Mar 6 19:58:38 2013 +0400
AGESA: Fix bug
Aladyshev Konstantin (ko...@list.ru) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2588
-gerrit
commit c0433f2abc380b68a1184782981da7f9c9a1c708
Author: Konstantin Aladyshev aladys...@nicevt.ru
Date: Wed Mar 6 19:58:38 2013 +0400
AGESA: Fix bug
Aladyshev Konstantin (ko...@list.ru) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2589
-gerrit
commit b319776457fc96a861e7e7fb92424c178cd7cef9
Author: Konstantin Aladyshev aladys...@nicevt.ru
Date: Wed Mar 6 21:39:40 2013 +0400
Supermicro
Paul Menzel (paulepan...@users.sourceforge.net) just uploaded a new patch set
to gerrit, which you can find at http://review.coreboot.org/2590
-gerrit
commit 7e972c8973f0e969c7c3a4073d3fdc0ccd65bef3
Author: Paul Menzel paulepan...@users.sourceforge.net
Date: Wed Mar 6 18:42:02 2013 +0100
Dear coreboot folks,
Jenkins seems to be configured to delete build logs after a certain
amount of time. For example #4000 is not there anymore [1].
I am aware that Jenkins has to build a lot of commits (and their
iterations). For archival purposes, I’d vote for keeping the logs, if
possible.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2585
-gerrit
commit 24adaa2017ee87adc3204affb2f98267d8790183
Author: Ronald G. Minnich rminn...@gmail.com
Date: Mon Mar 4 16:39:35 2013 -0800
google/snow: Change
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2592
-gerrit
commit 1480149869b2806153fd849cca2a85a8b26f1727
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Tue Mar 5 14:21:28 2013 -0700
Persimmon DSDT:
Aladyshev Konstantin (ko...@list.ru) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2591
-gerrit
commit 16b2edf6b25b92243be5669afa4dc3dacd1a0f4d
Author: Konstantin Aladyshev aladys...@nicevt.ru
Date: Wed Mar 6 22:13:42 2013 +0400
AGESA: Fix
the following patch was just integrated into master:
commit 3914a316c3d3ab1ba45fe33394f37aaefdc62d61
Author: Jens Rottmann jrottm...@lippertembedded.de
Date: Tue Feb 19 15:01:06 2013 +0100
AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
The power up default for the
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2592
-gerrit
commit a117e9fe56e89b95f3816da0497a6be58b2aafe2
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Tue Mar 5 14:21:28 2013 -0700
Persimmon DSDT:
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2592
-gerrit
commit c68348a6fce8959c8ae859415854a9d7f9a50c1b
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Tue Mar 5 14:21:28 2013 -0700
Persimmon DSDT:
the following patch was just integrated into master:
commit f4861df1e749885ec68ea0f17a3589aa6e79d13f
Author: Ronald G. Minnich rminn...@gmail.com
Date: Mon Mar 4 16:39:35 2013 -0800
google/snow: Change MMC0 to work in 8 bit mode.
The MMC0 on google/snow can run in 8 bit mode. To
On Sun, 3 Mar 2013 22:58:46 -0500
ron minnich rminn...@gmail.com wrote:
setgtt is only for hardware with a gtt. Again, I'm not familiar with
the hardware on this laptop. Does it have a gtt?
it seems so(from the xf86-video-intel mentioned before):
if (IS_G4X(pI830))
gtt =
On Sat, Mar 2, 2013 at 2:07 AM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear coreboot folks,
please take a look at the following difference of two files.
$ diff -u src/southbridge/amd/cimx/sb{8,9}00/late.c
--- src/southbridge/amd/cimx/sb800/late.c
Unless you're prepared to test and verify on the exact hardware, don't
do it. We've had lots of well-intentioned efforts like this over the
years that broke platforms. I don't like finding that somebody has
broken a platform 2 years after a cosmetic improvement of this sort
was made. And that has
the following patch was just integrated into master:
commit 31dc0acd9b8c3e5d30aa4e64ab1f24fac84bac1a
Author: Ronald G. Minnich rminn...@gmail.com
Date: Wed Mar 6 08:50:50 2013 -0800
Google/Snow: enable sound hardware clocks
Set up the clocks used for sound and turn on the sound
the following patch was just integrated into master:
commit a4b802ce866a1f3397f0e93e530bf77e253f60ee
Author: Paul Menzel paulepan...@users.sourceforge.net
Date: Wed Mar 6 18:42:02 2013 +0100
ASRock E350M1: mainboard.c: Add declarations for `set_pcie_{,de}reset`
Since the merg of
David Hendricks wrote:
I suspect it's best to simply accept the ugly parts rather than
diverge from whatever AMD uses internally.
I think it depends. If the coreboot repo is basically a write-once
medium for the AMD code and if what gets written never has any reuse
anyway then I think it would
Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2570
-gerrit
commit 7511d877db3bcf7a3ccd9073932ee775f61ca78c
Author: Ronald G. Minnich rminn...@gmail.com
Date: Fri Mar 1 10:18:14 2013 -0800
the following patch was just integrated into master:
commit 6bde149d9c56a824eff5db7bb06d7c386fb2be30
Author: Ronald G. Minnich rminn...@gmail.com
Date: Fri Mar 1 10:18:14 2013 -0800
samsung/exynos5: add display port and framebuffer defines and initialization
These are essential
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2592
-gerrit
commit 969e55b868fd2fcb5e02cde02447a894f158245b
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Tue Mar 5 14:21:28 2013 -0700
Persimmon DSDT:
the following patch was just integrated into master:
commit e988b515f11fa9483fc5209a9894b8d485525a61
Author: Paul Menzel paulepan...@users.sourceforge.net
Date: Sat Feb 23 00:15:49 2013 +0100
ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`
Quoting Jens
the following patch was just integrated into master:
commit 5a22b14d47955a2cce1d51d883a3c0ee4df39df0
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Tue Feb 26 13:49:56 2013 +0200
Fix socket LGA775
Models 6ex and 6fx select UDELAY_LAPIC so cannot select
contradicting
the following patch was just integrated into master:
commit 41dd3dbd5e5619b9957de6850541af7cfe21a1a8
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Tue Jul 3 11:36:44 2012 +0300
Intel e7505: provide get_top_of_ram
This is required to enable EARLY_CBMEM_INIT.
the following patch was just integrated into master:
commit d59fc5340ea2fc12f6cf98a2e2166435869f0d3c
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date: Thu Feb 28 00:32:25 2013 +0200
Fix build by adding `cbmem.c` to `COLLECT_TIMESTAMPS`
A board without HAVE_ACPI_RESUME did not
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2600
-gerrit
commit ca10347d23dc11e0873279cba6dfcd194930fef3
Author: David Hendricks dhend...@chromium.org
Date: Thu Mar 7 00:58:10 2013 +0100
Revert ARMv7:
Stefan Reinauer (stefan.reina...@coreboot.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2601
-gerrit
commit 99e484f98420d39d5a9b8f20e2d0de01dd00fa1e
Author: Stefan Reinauer reina...@chromium.org
Date: Wed Mar 6 15:56:14 2013 -0800
the following patch was just integrated into master:
commit 0f4c0e2669f76bf1081bf13019bc664b4f0e6b38
Author: Paul Menzel paulepan...@users.sourceforge.net
Date: Fri Feb 22 12:33:08 2013 +0100
src/arch/x86/boot/acpigen.c: Small coding style and comment fixes
While reading through
* Jens Rottmann jrottm...@lippertembedded.de [130306 17:29]:
Hi Martin (and all),
I wrote:
You dereference dev in line 132, so if it's really 0,
will you then ever reach this check?? (I don't know if
in romstage *NULL is caught.)
You wrote:
yes, if it's 0, we still reach the code.
the following patch was just integrated into master:
commit 2323f3551fe630e33f7ef59f1309db56956af5d4
Author: Stefan Reinauer reina...@chromium.org
Date: Wed Mar 6 15:56:14 2013 -0800
google/snow: fix coding style
cosmetics
Change-Id:
On 03/06/2013 09:29 AM, Jens Rottmann wrote:
Hi Martin (and all),
I wrote:
You dereference dev in line 132, so if it's really 0,
will you then ever reach this check?? (I don't know if
in romstage *NULL is caught.)
You wrote:
yes, if it's 0, we still reach the code. I've changed it
to not
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2602
-gerrit
commit 0ab3fec064562b446c232d37de158a69d646182c
Author: David Hendricks dhend...@chromium.org
Date: Wed Mar 6 20:11:20 2013 -0800
exynos5: add
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2603
-gerrit
commit 5a33377f33c6a8d38287fa9b2795f8909f28da00
Author: David Hendricks dhend...@chromium.org
Date: Wed Mar 6 19:16:10 2013 -0800
snow: add real
I'm not convinced.
ron
On Wed, Mar 6, 2013 at 9:48 AM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear coreboot folks,
Jenkins seems to be configured to delete build logs after a certain
amount of time. For example #4000 is not there anymore [1].
I am aware that Jenkins has to
the following patch was just integrated into master:
commit 1d290eeb1c72a31b5d49a1fca57f99b081fe24d4
Author: David Hendricks dhend...@chromium.org
Date: Wed Mar 6 20:11:20 2013 -0800
exynos5: add GPIO port enums
This adds an enum for GPIO ports on the Exynos5. To make them
the following patch was just integrated into master:
commit d9b16f3b048243fd7d4c4513875f7f241261ce50
Author: David Hendricks dhend...@chromium.org
Date: Wed Mar 6 19:16:10 2013 -0800
snow: add real values for GPIOs in fill_lb_gpios()
This adds some real GPIO mappings where virtual
the following patch was just integrated into master:
commit 147cdc3b171c8f02434dc3b6bbd70b6406de93ee
Author: David Hendricks dhend...@chromium.org
Date: Thu Mar 7 00:58:10 2013 +0100
Revert ARMv7: Simplify div64
This reverts commit 1cd616082100f47dc2d6d73669c6aa2e5eb039ad
On Wed, Mar 6, 2013 at 8:29 AM, Jens Rottmann
jrottm...@lippertembedded.de wrote:
Per default, after any *ptr, GCC assumes a SEGFAULT would occur if ptr was
==0, so if control flow does reach the following code ptr must be !=0. ==
After any *ptr GCC will optimize away all ptr==0 or !=0
On Thu, Mar 7, 2013 at 12:38 AM, ron minnich rminn...@gmail.com wrote:
I'm not convinced.
ron
On Wed, Mar 6, 2013 at 9:48 AM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear coreboot folks,
Jenkins seems to be configured to delete build logs after a certain
amount of time. For
Am 2013-03-07 07:10, schrieb Gregg Levine:
Ron, he's right. I just checked and it seems that everything including
that number is not at home. Perhaps there's a finite limit to how many
records the bot can work with?
It's limited because build logs get large quickly and we ran out of
disk space
44 matches
Mail list logo
