ron minnich wrote:
I'm not really happy that we're doing all this PIC setup for one OS,
It's not for one OS, Ron. PIC setup is part of the PC legacy.
Please remember that coreboot is more than Chrome OS' firmware of choice.
It's been quite some time since I've had to use PIC mode at all.
On Mon, May 12, 2014 at 09:13:26PM +0200, Peter Stuge wrote:
ron minnich wrote:
I'm not really happy that we're doing all this PIC setup for one OS,
It's not for one OS, Ron. PIC setup is part of the PC legacy.
Please remember that coreboot is more than Chrome OS' firmware of choice.
On Mon, May 12, 2014 at 12:13 PM, Peter Stuge pe...@stuge.se wrote:
Why shouldn't coreboot do legacy initialization? What is the reason
to be *less* compatible than possible?
The main question I had was whether enabling this set of interrupts
could negatively impact other payloads. The goal of
Dear coreboot folks,
when building coreboot without serial console for QEMU and when trying
to run the payloads Tint [1] (or coreinfo) in it, no graphics comes up
and the payloads are not loaded.
Just enabling serial console fixes the problem. Tinycurses is used in
libpayload as there were
Hi all,
1) we should provide at least the MP-Table. There is a still lot of OS without
ACPI support (various homebrew OS, RTOS etc) which don't want to carry the
ACPICA just to get idea how to route IRQs...
2) if we want to setup the PCI for PIC we need to do:
a) setup the PCI router (just
Like I say, if it's not going to do harm, and you all want it, submit the CL.
ron
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