Dear Wen,
Am Mittwoch, den 18.06.2014, 16:44 -0400 schrieb Wen Wang:
Which commit is the known good commit, and has been regressed?
you wrote it worked with the code from two weeks ago. So please use that
commit as the good commit. Though make sure that it really works. The
bad commit is the
Scott Duplichan [mailto:sc...@notabs.org] wrote:
]Sent: Thursday, January 09, 2014 08:37 AM
]To: 'coreboot@coreboot.org'
]Subject: coreboot engineer needed
]
]
]https://intel.taleo.net/careersection/1/jobdetail.ftl?job=725464
]
]Thanks,
]Scott
We were able to resolve this by enabling MSI interrupts in our PCIe core
and our Linux device driver.
Thanks go to Scott Duplichan for his helpful guidance.
Mark Mason
Engineering Design Team
We are testing coreboot with our new IMB-A180 based AGESA design,
and DMA interrupts are not
We have a board that is failing to boot, and we think there is a memory
problem on the board. I have a trace (od -t x4 dump) of the POST codes:
000 01 10 10 a0 a1 a1 30 31 34 37 c0 b1 c1 38 39 c4
020 71 72 75 76 77 78 79 7b 7a 7c 90 91 91 58 5a 01
040 10 10 a0 a1 a1 34 37 c0 c1 38
On 06/17/2014 01:12 AM, Christian Gmeiner wrote:
2014-06-16 19:05 GMT+02:00 Rafael Vanoni rafael.van...@pluribusnetworks.com:
On 06/13/2014 09:40 AM, Marc Jones wrote:
Rafael,
i don't think that you can update them once the OS loads. The OS would
have already made decisions based on the
Rafael Vanoni wrote:
is there a tool or library to edit DMI values ?
No.
Please explain why you want to modify these values at run time?
//Peter
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Mark,
Can you describe your memory SODIMM config?
Are you loading both SODIMMs?
An engineer here suggests you set BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE
in the mainboard buildOpts.c file.
Thanks,
Dave
On Thu, Jun 19, 2014 at 12:37 PM, Mark C. Mason m...@edt.com wrote:
We have a board that is
Dave,
Dave Frodin wrote:
An engineer here suggests you set BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE
in the mainboard buildOpts.c file.
Can you please provide more information.
I think it is incredibly embarrassing that coreboot has code which
requires manually messing with #defines depending on
Mark C. Mason wrote:
We were able to resolve this by enabling MSI interrupts in our PCIe core
and our Linux device driver.
That's a good workaround, but clearly doesn't actually resolve the
problem. The problem still exists; coreboot fails to initialize the
system completely in some cases.
I
Mark,
You may want to look at two patches that are still in review...
http://review.coreboot.org/#/c/6065/ ports the CIMX changes to agesa
http://review.coreboot.org/#/c/5948/ makes use of the PCI INT support on
hp/abm (as an example)
Dave
On Thu, Jun 19, 2014 at 1:42 PM, Peter Stuge
Peter,
It was intended as a debug step. That engineer is working
through similar issues on a similar chipset that has problems
with multiple DIMMs and suggested it be tried.
Dave
On Thu, Jun 19, 2014 at 1:33 PM, Peter Stuge pe...@stuge.se wrote:
Dave,
Dave Frodin wrote:
An engineer here
On 06/19/2014 12:25 PM, Peter Stuge wrote:
Rafael Vanoni wrote:
is there a tool or library to edit DMI values ?
No.
Please explain why you want to modify these values at run time?
//Peter
Like I said in a previous post, I'd like to set fields like version,
serial number on a per
I went back to the commit (Martin's commit
d75800c7f2476bee243cc22255acb54d6676d4bc back in late May) that seems work
for a few people on the list. I also thought it was working better for me
too as I was observing coreboot and fsp booting until it failed at SeaBIOS.
It turned out I had a pilot
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