Hi,
I have an IBM ThinkPad T60 laptop(1951-CTO) which uses BIOS(version
2.27) from Phoenix Technologies. I would like to replace this with
Coreboot and use SeaBIOS as a payload as I need to change the order of
boot devices from time to time. I do not need SeaBIOS for BIOS
callback functions as I
Martin T wrote:
What is the correct definition of my flash chip in flashchips.c file?
.name = MX25L1605D/MX25L1608D,
This one.
I wasn't able to find the exact data sheet.
Look for MX25L1605D.
//Peter
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.model_id 0x14
.probe probe_spi_res1
.write spi_chip_write_1
On 08/07/14 15:26, Peter Stuge wrote:
Martin T wrote:
What is the correct definition of my flash chip in flashchips.c
file?
.name = MX25L1605D/MX25L1608D,
This one.
I had not seen this, maybe you all have, but:
http://inertiawar.com/microcode/
ron
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Hello!
No I haven't. But I've known about the Intel Microcode update idea for
about fifteen years. Turns out that the Linux Kernel 2.4.33.2 of
course has it, and described the update process. The two responsible
for that method have been out of business so to speak for a while now.
But according
you can no longer update microcode after the kernel boots (on modern Intel
CPUs). It has to happen before you do Cache As Ram in many cases, or you'll
get some pretty unpleasant consequences.
ron
On Tue, Jul 8, 2014 at 9:34 AM, Gregg Levine gregg.drw...@gmail.com wrote:
Hello!
No I haven't.
On Tue, Jul 8, 2014 at 10:39 AM, ron minnich rminn...@gmail.com wrote:
you can no longer update microcode after the kernel boots (on modern Intel
CPUs). It has to happen before you do Cache As Ram in many cases, or you'll
get some pretty unpleasant consequences.
so even microcode_early will
no, that is not early enough on some CPUs.
ron
On Tue, Jul 8, 2014 at 11:20 AM, yhlu yingha...@gmail.com wrote:
On Tue, Jul 8, 2014 at 10:39 AM, ron minnich rminn...@gmail.com wrote:
you can no longer update microcode after the kernel boots (on modern
Intel
CPUs). It has to happen
ron minnich [mailto:rminn...@gmail.com] wrote:
]you can no longer update microcode after the kernel boots
](on modern Intel CPUs). It has to happen before you do Cache
]As Ram in many cases, or you'll get some pretty unpleasant
]consequences.
]
]ron
]
][...]
While I am no expert on recent
Yes, and that's sensible for some cases, if you consider that people don't
always keep their firmware up to date!
To be honest, I'm trying a little bit to discourage the idea that it's safe
to build coreboot without microcode blobs on modern CPUs. Might work on
your x60. Not recommended on more
Hello!
Agreed on all points.
Now Scott, I'm certainly no expert on Intel processors either, but in
a word, Thank you!, regarding all of that searching and finding out
where that stuff is based.
-
Gregg C Levine gregg.drw...@gmail.com
This signature fought the Time Wars, time and again.
On
ron minnich wrote:
To be honest, I'm trying a little bit to discourage the idea that it's safe
to build coreboot without microcode blobs on modern CPUs. Might work on
your x60. Not recommended on more recent chipsets. Yes, you might get it to
boot. That's almost worse than having it fail.
I
On Tue, Jul 8, 2014 at 1:07 PM, Peter Stuge pe...@stuge.se wrote:
I think very specific details would strengthen this argument. I'm not
saying that the argument is wrong, I'm saying that it would be great
to learn about specific experience.
you are absolutely right. I'm just trying to
Am 08.07.2014 20:57, schrieb ron minnich:
Might work on your x60. Not recommended on more recent chipsets. Yes,
you might get it to boot. That's almost worse than having it fail.
For a not-so-recent example, some of the later Via processors require a
microcode update lest they hang when you
Thanks for the good examples, Patrick.
So I'll say it one more time: while I understand the concerns about the
microcode blob, and I appreciate the sincerity of those who want to build
coreboot images that don't have them, I think it's a huge mistake to take
that path on almost anything made in
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