Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Aaron Durbin via coreboot
On Thu, Mar 19, 2015 at 7:53 PM, Julius Werner wrote: >> 145a8a: 83 c3 14add$0x14,%ebx > > Okay, sorry, I didn't know you looked that closely into this. That's > quite unrefuteable. > > The only question that I still have is then WTF the compiler was > thinking... this

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Julius Werner
> 145a8a: 83 c3 14add$0x14,%ebx Okay, sorry, I didn't know you looked that closely into this. That's quite unrefuteable. The only question that I still have is then WTF the compiler was thinking... this just sounds like a plain bug somewhere (but I agree that doesn't r

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Aaron Durbin via coreboot
On Thu, Mar 19, 2015 at 7:21 PM, Julius Werner wrote: >> That said, I went back and looked at the assembly dump. It was using >> 0x14 as the size of the structure when sequencing through the entries. >> >> 001465dc R _bs_init_begin >> 001465e0 r cbmem_bscb >> 00146600 r gcov_bscb >> 0014663c R _bs

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Timothy Pearson
On 03/19/2015 09:21 PM, Julius Werner wrote: That said, I went back and looked at the assembly dump. It was using 0x14 as the size of the structure when sequencing through the entries. 001465dc R _bs_init_begin 001465e0 r cbmem_bscb 00146600 r gcov_bscb 0014663c R _bs_init_end Each *entry* was

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Julius Werner
> That said, I went back and looked at the assembly dump. It was using > 0x14 as the size of the structure when sequencing through the entries. > > 001465dc R _bs_init_begin > 001465e0 r cbmem_bscb > 00146600 r gcov_bscb > 0014663c R _bs_init_end > > Each *entry* was aligned to 0x20. Just aligning

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Aaron Durbin
On Thu, Mar 19, 2015 at 3:54 PM, Julius Werner wrote: >> You are right that it would work, but back solving for which alignment >> the compiler decided is hard. It's definitely whack-a-mole in that >> case. It could have very well decided 16 too. Without any insight as >> to why that breaks down.

Re: [coreboot] Enabling SeaBIOS

2015-03-19 Thread Julius Werner
All ChromiumOS firmware components and support tools are open source (minus vendor blobs on certain platforms). The 'crossystem' and 'futility' (which contains 'gbb_utility' which is called by the set_gbb_flags.sh script) tools are part of https://chromium.googlesource.com/chromiumos/platform/vboot

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Julius Werner
> You are right that it would work, but back solving for which alignment > the compiler decided is hard. It's definitely whack-a-mole in that > case. It could have very well decided 16 too. Without any insight as > to why that breaks down. Or you go the route of putting alignments on > structures j

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Aaron Durbin
On Thu, Mar 19, 2015 at 5:29 PM, Julius Werner wrote: > Sounds like this could've been solved with a simple ALIGN(8) in the > ldscript, right? I don't know what made the compiler think that it > would have to align i386 pointers to 8 byte (which seems to be what > happened), but if it makes that d

Re: [coreboot] GCC update broke AMD Fam10h boot

2015-03-19 Thread Julius Werner
Sounds like this could've been solved with a simple ALIGN(8) in the ldscript, right? I don't know what made the compiler think that it would have to align i386 pointers to 8 byte (which seems to be what happened), but if it makes that decision then it should also conclude that sizeof(struct boot_st

[coreboot] 0xE0000/0xF0000 segment issue

2015-03-19 Thread Naresh G. Solanki
Hi All, I'm trying to port coreboot with seabios payload. Everything goes fine till the control is transferred to payload. Since payload is loaded between memory range 0xC_ - 0x10_. The problem I was facing was that the board was going to auto reboot mode while executing payload.. Once

Re: [coreboot] VGA doesn't work on Mohon Peak

2015-03-19 Thread Marc Jones
Hi Viktor, On Thu, Mar 19, 2015 at 4:23 AM Kuzmichev Viktor wrote: > Hello, > > I'm using coreboot + SeaBIOS on Mohon Peak CRB. And I've tried to make > VGA work for a while now. I used this article as a guide: > http://www.coreboot.org/VGA_support > > Since it is an add-in card, you don't need

Re: [coreboot] VGA doesn't work on Mohon Peak

2015-03-19 Thread WANG FEI
Viktor, I've messed around VGA function on my platform before, I got the problem to display seabios messages on VGA as well, finally I fed up and enabled the bootsplash in coreboot instead, as along as the coreboot splash can be shown on monitor, which proves the VGA function works, it's what I wan

[coreboot] VGA doesn't work on Mohon Peak

2015-03-19 Thread Kuzmichev Viktor
Hello, I'm using coreboot + SeaBIOS on Mohon Peak CRB. And I've tried to make VGA work for a while now. I used this article as a guide: http://www.coreboot.org/VGA_support Extracting VGA BIOS from vendor BIOS image did not work: $ ./bios_extract EDVLCRB1.86B.0043.R00.1408290947_MPK.bin Using f