Re: [coreboot] coreboot community chat

2015-05-20 Thread Stefan Reinauer
Quick reminder: This is coming up tomorrow (about 18h from now) Looking forward to seeing you all Stefan * Stefan Reinauer [150507 06:05]: > Hi coreboot community! > > In order to have more face time and a more personal connection with each > other than it is possible on the coreboot IRC chann

Re: [coreboot] SPD CRC failed

2015-05-20 Thread David Hendricks via coreboot
On Wed, May 20, 2015 at 1:13 PM, Michael Gerlach wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > I forgot to mention that somehow the ram frequency is not detected > correctly... > > PLL busy...done > PLL didn't lock. Retrying at lower frequency > PLL busy...done > PLL didn't lock.

Re: [coreboot] [RFC] Preparing a crowdfunding campaign for the ASUS KGPE-D16

2015-05-20 Thread The Gluglug
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 17/05/15 15:11, Paul Menzel wrote: > Dear coreboot folks, > > > Timothy, congratulations again on making a coreboot port for the > ASUS KGPE-D16 and therefore completing your third coreboot port! > That’s really amazing! > > > Am Mittwoch, den

Re: [coreboot] SPD CRC failed

2015-05-20 Thread Michael Gerlach
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi! I added debug statements (http://pastebin.com/iSFstXmv) and realized that the calculated checksum is 0.. CLC_CRC : 0 SPD_CRC : ce66 Furthermore I had a look at src/device/dram/ddr3.c line 155 - The capacity is given with 4GB (as you see in the l

Re: [coreboot] SPD CRC failed

2015-05-20 Thread Michael Gerlach
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I forgot to mention that somehow the ram frequency is not detected correctly... PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at lower frequency PLL busy...done PLL didn't lock. Retrying at l

Re: [coreboot] SPD CRC failed

2015-05-20 Thread Timothy Pearson
On 05/20/2015 12:46 PM, Michael Gerlach wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS... Unfortunately I do not have any other DDR3 modules to test. Best regard

Re: [coreboot] SPD CRC failed

2015-05-20 Thread Michael Gerlach
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I guess this check is done by Lenovo BIOS in a different way? Because this board+ram has no problems booting with vendor BIOS... Unfortunately I do not have any other DDR3 modules to test. Best regards, n3ph On 05/20/15 19:20, Vadim Bendebury wro

Re: [coreboot] SPD CRC failed

2015-05-20 Thread Vadim Bendebury
SPD is some data saved on the memory module, available to the processor to read to find out memory properies. These data are protected by a check code (CRC) which allows the CPU to verify that it read the data correctly. Apparently this check is failing in your case. Some likely reasons could be

[coreboot] SPD CRC failed

2015-05-20 Thread Michael Gerlach
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi all, i was testing coreboot on lenovo x230 with 2x8G DDR3.. Seems like there are some issues regarding the size of the modules.. http://pastebin.com/mLcS6vhQ Best regards, n3ph -BEGIN PGP SIGNATURE- Version: GnuPG v2 iQEcBAEBAgAGBQJVXK