On 08.06.2016 04:26, Naveed Ghori wrote:
> Thanks Nico,
> What options should I be looking to tune? 3Gig should be fine as that
> is what I have seen in another product.
>
This depends heavily on the used hardware platform. I don't think all of
them have an option in coreboot. But it might be just
On 07.06.2016 16:40, Patrick Rudolph wrote:
> On 2016-06-06 09:58 PM, ron minnich wrote:
>> On Mon, Jun 6, 2016 at 12:52 PM Patrick Rudolph
>> wrote:
>>
>>> To summarize:
>>> The easy way is to use 2G.
>>> The preferred way would be to mimic mrc behaviour and reboot after
>>> finding the correct s
Hi,
> > There's a known failure case.
> > If someone puts in multiple PCI cards that uses more than 2GB of mmio
> > it'll break again.
> And what will happen if you need more than 3GiB MMIO space? more than
> 4GiB? ... you have to set a limit somewhere. And that can be confi-
> gurable, IMO (It
On 06/07/16 16:35, Zoran Stojsavljevic wrote:
>> Note that you can build seabios as CSM for tianocore already.
>
> These are the opposites: SeaBIOS is CSM ON (emulates Leagcy BIOS), while
> Tiano Core supposed to be CSM OFF (UEFI), Thus, SeaBIOS and Tiano Core
> exclude each other (should not be u
A new post titled "[GSoC] Multiple status register support, week #1 and #2" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/06/07/gsoc-multiple-status-register-support-week-1-and-2/
Hi, I am Hatim Kanchwala (hatim on IRC) from India. I am the GSoC
A new post titled "[GSoC] Better RISC-V support, week #2" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/06/06/gsoc-better-risc-v-support-week-2/
Last week, I updated my copy of spike (to commit 2fe8a17a), and familiarized myself with the differe
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