+1 Julius. As an extra note you should also remember master can only
enter writing mode after reading mode and slave can enter into reading
mode only after writing mode.
On Sat, Oct 8, 2016 at 6:21 AM, Julius Werner wrote:
> I2C is a very simple bus format with some common conventions attached
>
I2C is a very simple bus format with some common conventions attached
to it that are followed by most (but not all) devices. You can find a
pretty good summary of how it works on Wikipedia:
https://en.wikipedia.org/wiki/I2C
For devices which follow this convention, the device exposes registers
tha
Dear Samuthria,
when you configure a pin as PAD_VAL_OUTPUT, it's input function will be
disabled and you will read always 0. I assume that the hw-pin will toggle,
if you measure it.
Please configure this pin as 'PAD_VAL_OUTPUT_ENABLE' instead of
'PAD_VAL_OUTPUT', since this will let the input d
On Fri, Oct 7, 2016 at 8:28 AM, Trammell Hudson wrote:
> On Thu, Oct 06, 2016 at 11:27:01AM -0700, Duncan Laurie wrote:
> > I may be mis-remembering and this might come up as ttyS0 in linux for
> > skylake. (it is ttyS2 on apollolake...) Or just use a custom command
> line
> > like console=uart
I apologize that my questions are not about coreboot and I am sort of hijacking
the forum. But I think that this is a place where people with good knowledge of
the hardware can be found. Maybe my issue will be of interest to you as well.
And I hope to get some help. Maybe even some secrets shar
On Thu, Oct 06, 2016 at 11:27:01AM -0700, Duncan Laurie wrote:
> I may be mis-remembering and this might come up as ttyS0 in linux for
> skylake. (it is ttyS2 on apollolake...) Or just use a custom command line
> like console=uart,mmio32,0xd1134000,115200n8
That commandline doesn't produce any o
I checked out the coreboot code last time with debug traces that I have
on my platform.
In addition I read the atom e3800 family datasheet (from intel website).
I look at these files:
https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytrail/gpio.c
https://review.coreboot.org/c
Hi,
Please find the latest report on new defect(s) introduced to coreboot found
with Coverity Scan.
1 new defect(s) introduced to coreboot found with Coverity Scan.
49 defect(s), reported by Coverity Scan earlier, were marked fixed in the
recent build analyzed by Coverity Scan.
New defect(s)
Hello Сheng. Quote from mailing list: > I try to enable Lpss device(i2c hs-uart) with ACPI mdoe.> i2c and hs-uart will show yellow mark in device manager with win8.1.> but I can't find the same issue in intel coreboot(versrion MR5). Have you solved the problem with LPSS device in ACPI mode for Wind
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