Hi,
On 02/13/2017 11:16 AM, Nico Huber wrote:
On 13.02.2017 08:19, Andrey Petrov wrote:
For example Apollolake is struggling to finish firmware boot with all
the whistles and bells (vboot, tpm and our friendly, ever-vigilant TXE)
under one second.
Can you provide exhaustive figures, which part
Hi All,
We started looking at doing things in parallel speed the boot process and meet
the ChromeOS boot time requirements. One of the larger portions of boot time
is memory initialization which is why we are considering doing parallelism
early.
On Chromebooks, the Intel boot path is using bo
By the way, there are also Opteron 6276's (16C 2,3GHz) for 49,- EUR
each from two german sellers.
On Tue, 14 Feb 2017 14:45:36 -0500
"taii...@gmx.com" wrote:
> I thought people might want to know:
>
> There's three opteron 6287SE's on ebay for $300 each and the seller
> also has best offer, t
On Tue, Feb 14, 2017 at 1:07 PM, Patrick Georgi wrote:
> 2017-02-14 17:12 GMT+01:00 Aaron Durbin via coreboot :
>> For an optimized bootflow
>> all pieces of work that need to be done pretty much need to be closely
>> coupled. One needs to globally optimize the full sequence.
> Like initializing s
Listen Timothy
INTEL is FW (we can argue here, I do agree) and SW (NOT at all any
argument, it is an aksioma) very crappy company. I know that INTEL CCG
directors ordered people to watch me over, and, personally, I do NOT care.
Really I don't. I worked for 5 years for INTEL support in Bavaria.
On Tue, Feb 14, 2017 at 1:06 PM, Nico Huber wrote:
> On 14.02.2017 18:56, ron minnich wrote:
>> At what point is ramstage a kernel? I think at the point we add file
>> systems or preemptive scheduling. We're getting dangerously close. If we
>> really start to cross that boundary, it's time to reth
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On 02/14/2017 01:36 PM, Zoran Stojsavljevic wrote:
>> Where do we go from here?
>
> As I said (and I'll repeat, many times, if required - I do NOT care what
> all INTEL [all their 13000+ managers] think):
>
> /I have another idea for INTEL SoCs/CPUs,
I thought people might want to know:
There's three opteron 6287SE's on ebay for $300 each and the seller also has
best offer, they are a foreign seller but the ebay money back guarantee applies.
It is the fastest g34 cpu made and apparently it was only ever sold to a small
amount of OEM's so i
> Where do we go from here?
As I said (and I'll repeat, many times, if required - I do NOT care what
all INTEL [all their 13000+ managers] think):
*I have another idea for INTEL SoCs/CPUs, as HW architecture improvement.
Why your top-notch HW guys do NOT implement MRC as part of MCU. Some HW
thre
2017-02-14 17:12 GMT+01:00 Aaron Durbin via coreboot :
> For an optimized bootflow
> all pieces of work that need to be done pretty much need to be closely
> coupled. One needs to globally optimize the full sequence.
Like initializing slow hardware even before RAM init (as long as it's
just an init
On 14.02.2017 18:56, ron minnich wrote:
> At what point is ramstage a kernel? I think at the point we add file
> systems or preemptive scheduling. We're getting dangerously close. If we
> really start to cross that boundary, it's time to rethink the ramstage in
> my view. It's not a good foundation
On Tue, Feb 14, 2017 at 11:56 AM, ron minnich wrote:
> Just a reminder about times past. This discussion has been ongoing since
> 2000. In my view the questions come down to how much the ramstage does, how
> that impacts code complexity and performance, and when the ramstage gets so
> much capabil
Just a reminder about times past. This discussion has been ongoing since
2000. In my view the questions come down to how much the ramstage does, how
that impacts code complexity and performance, and when the ramstage gets so
much capability that it ought to be a kernel.
In the earliest iteration,
On Mon, Feb 13, 2017 at 1:16 PM, Nico Huber wrote:
> On 13.02.2017 08:19, Andrey Petrov wrote:
>> For example Apollolake is struggling to finish firmware boot with all
>> the whistles and bells (vboot, tpm and our friendly, ever-vigilant TXE)
>> under one second.
> Can you provide exhaustive figur
On Mon, Feb 13, 2017 at 9:32 PM, ron minnich wrote:
> andrey, great questions. If you're really concerned about those issues, then
> yes, maybe a space sharing solution is the right one.
>
> I really would rather not see people implementing schedulers at this point.
> If we're going to go that rou
On Mon, Feb 13, 2017 at 5:28 PM, Julius Werner wrote:
> +1 for preferring a single-core concurrency model. This would be much more
> likely to be reusable for other platforms, and much simpler to maintain in
> the long run (way less platform-specific details to keep track of and figure
> out again
On Mon, Feb 13, 2017 at 8:43 PM, Andrey Petrov wrote:
> Hi,
>
> On 02/13/2017 12:31 PM, ron minnich wrote:
>>
>> Another idea just popped up: Performing "background" tasks in udelay()
>> / mdelay() implementations ;)
>>
>>
>> that is adurbin's threading model. I really like it.
>>
>> A lot
On Mon, Feb 13, 2017 at 8:05 AM, Peter Stuge wrote:
> Andrey Petrov wrote:
>> We are considering adding early parallel code execution in coreboot.
>> We need to discuss how this can be done.
>
> No - first we need to duscuss *if* this should be done.
>
>
>> Nowadays we see firmware getting more co
The ASUS KFSN4-DRE fails verification for branch master as of commit
e2143cdf5a95032809449722950e503740973a56
The following tests failed:
BOOT_FAILURE
Commits since last successful test:
e2143cd AGESA: Remove nonexistent include path
See attached log for details
This message was automatically
Hello Andrey,
I found that Coreboot really implements atomic and semaphores operations?!
What for? Did not expect to find these... At all???
The ONLY reason why, is that in some SoCs are going some independent
(invisible) HW threads using the same resources as BSP core (all other
cores should be
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